Patents by Inventor Chien-Ming Lan

Chien-Ming Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9075103
    Abstract: Provided is a test structure for wafer acceptance test (WAT). The test structure includes a row of a plurality of first pads electrically connecting to each other, a second pad, a third pad, a first peripheral metal line, and a second peripheral metal line. The second pad is disposed in the vicinity of a first end of the row, wherein the second pad is electrically disconnected to the first pads. The third pad is disposed in the vicinity of a second end of the row, wherein the third pad is electrically disconnected to the first pads. The first peripheral metal line is disposed at a first side of the row and electrically connected to the second pad. The second peripheral metal line is disposed at a second side of the row and electrically connected to the third pad.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: July 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Qiong Wu, Chien-Ming Lan
  • Publication number: 20140097862
    Abstract: Provided is a test structure for wafer acceptance test (WAT). The test structure includes a row of a plurality of first pads electrically connecting to each other, a second pad, a third pad, a first peripheral metal line, and a second peripheral metal line. The second pad is disposed in the vicinity of a first end of the row, wherein the second pad is electrically disconnected to the first pads. The third pad is disposed in the vicinity of a second end of the row, wherein the third pad is electrically disconnected to the first pads. The first peripheral metal line is disposed at a first side of the row and electrically connected to the second pad. The second peripheral metal line is disposed at a second side of the row and electrically connected to the third pad.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Inventors: Qiong Wu, Chien-Ming Lan
  • Patent number: 7741198
    Abstract: A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: June 22, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Chien-Ming Lan
  • Patent number: 7456479
    Abstract: A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 25, 2008
    Assignee: United Microelectronics Corp.
    Inventor: Chien-Ming Lan
  • Publication number: 20080258748
    Abstract: A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern.
    Type: Application
    Filed: June 29, 2008
    Publication date: October 23, 2008
    Inventor: Chien-Ming Lan
  • Publication number: 20070141841
    Abstract: A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 21, 2007
    Inventor: Chien-Ming Lan