Patents by Inventor Chien-Ming Lee

Chien-Ming Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120269652
    Abstract: A control method of a fan rotation speed, which controls the operation of a fan set including fans connected in series, is disclosed. The control method includes the steps of acquiring a control factor; judging whether the control factor is less than a first threshold value; executing a first control procedure when the control factor is less than the first threshold value; judging whether the control factor is greater than a second threshold value when the control factor is greater than the first threshold; executing a second control procedure when the control factor is greater than the second threshold value; and executing a third control procedure when the control factor is less than the second threshold value.
    Type: Application
    Filed: July 19, 2011
    Publication date: October 25, 2012
    Inventors: Chia-Ming HSU, Chien-Ming LEE, Yueh-Lung HUANG, Jung-Yuan CHEN, Ching-Sen HSIEH, Chia-Lin LEE, Yen-Hung CHEN, Jian-Cun LIN
  • Patent number: 7961916
    Abstract: The present invention provides an identification method. A video capture device captures an identification video at a random time. Then a suitable identification image is obtained from the identification video. Subsequently, a current user characteristic value obtained from the identification image is compared with a stored user characteristic value of a user data stored in a recognition database. When the current user characteristic value corresponds to the stored user characteristic value, then returns to capture the identification video step. When the current user characteristic value does not corresponds to the stored user characteristic value, then an error counter is incremented, and returns to the acquiring the identification video step.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: June 14, 2011
    Assignee: Compal Electronics, Inc.
    Inventors: Jen-Li Wang, Chien-Ming Lee
  • Publication number: 20110128899
    Abstract: An electronic device and a power saving method thereof are provided. The electronic device includes a network module and a power saving module, wherein the network module connects to an access point (AP). The method includes executing an AP search operation at a predetermined time interval by the network module, and determining whether the electronic device is in a specific state by the power saving module. The method also includes disabling the network module from executing the AP search operation as long as the electronic device is still in the specific state. As a result, the unnecessary AP search operations can be avoided, and the purpose of saving power can be achieved.
    Type: Application
    Filed: October 29, 2010
    Publication date: June 2, 2011
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Ta Su, Hsin-Hung Lin, Der-Chung Hwang, Anhua Tsui, Chieh-Tsao Hwang, Chih-Wei Chang, Jenq-Haur Pan, Shao-Hsien Wang, Chien-Ming Lee
  • Patent number: 7667359
    Abstract: A stator structure includes a first cover, a stator assembly and a filler. The first cover has an accommodation space for accommodating the stator assembly therein. The filler is applied between the first cover and the stator assembly to surround the stator assembly. A manufacturing method of the stator structure is also disclosed.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: February 23, 2010
    Assignee: Delta Electronics, Inc.
    Inventors: Chien-Ming Lee, Deng-Chu Fu, Ying-Chi Chen, Wen-Shi Huang
  • Patent number: 7397642
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit, and a trigger current generator. The object of the stacked MOS circuit is to be the first releasing path of the ESD current; the object of the trigger current generator is to generate the trigger current to turn on the stacked MOS circuit, and then the stacked MOS circuit would be the first releasing path of the ESD current.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: July 8, 2008
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ming-Dou Ker, Chien-Ming Lee
  • Publication number: 20080145246
    Abstract: A fan includes a motor base, a motor, an impeller, and a fan housing. The fan housing accommodates the motor base, the impeller, and the motor, and includes at least one flapper disposed at the corner of the fan housing via a plurality of connecting elements for covering the opening of the fan housing to prevent the air backflow.
    Type: Application
    Filed: December 13, 2007
    Publication date: June 19, 2008
    Inventors: Chien-Ming LEE, Ying-Chi CHEN
  • Patent number: 7371448
    Abstract: This invention discloses a novel rewritable phase-change recording medium for optical data storage, which is based on the GaSbTe ternary alloy system. The designed compositions reside on the Sb7Te3—GaSb and Sb2Te3—GaSb pseudo-binary tielines, and the claimed region can be expressed by the formula (SbxTe100-x)1-z(GaySb100-y)z, 35?x?80, 40?y?50, 0.05?z?0.9. The crystallized phase of the GaSbTe films is a single phase after laser annealing, and the crystal structure is hexagonal with continuous variation in lattice constants. The lattice parameters, a is from 4.255 ? to 4.313 ? and c is from 11.200 ? to 11.657 ?, corresponding to the c/a ratio 2.60 to 2.73. The crystallization kinetics shows increased crystallization temperature (181 to 327° C.) and activation energy (2.8 to 6.5 eV) with increasing GaSb content.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: May 13, 2008
    Assignee: National Tsing Hua University
    Inventors: Tsung Shune Chin, Chien Ming Lee
  • Publication number: 20080049985
    Abstract: The present invention provides an identification method. A video capture device captures an identification video at a random time. Then a suitable identification image is obtained from the identification video. Subsequently, a current user characteristic value obtained from the identification image is compared with a stored user characteristic value of a user data stored in a recognition database. When the current user characteristic value corresponds to the stored user characteristic value, then returns to capture the identification video step. When the current user characteristic value does not corresponds to the stored user characteristic value, then an error counter is incremented, and returns to the acquiring the identification video step.
    Type: Application
    Filed: June 4, 2007
    Publication date: February 28, 2008
    Inventors: Jen-Li Wang, Chien-Ming Lee
  • Publication number: 20080036978
    Abstract: A projecting apparatus includes a power, a lamp, and a thermal controlling module. The lamp is energized from the power. The thermal controlling module includes a blower, an air duct, and a thermal break. The blower and an air duct, which connects the lamp and the blower, are for making and directing airflow through the lamp. The thermal break is electrically connected to the power and the lamp, and is disposed on the air duct and positioned adjacent the lamp. When the temperature in the projecting apparatus exceeds a predetermined value, the thermal break becomes a turnoff so as to allow the projecting apparatus to be shut off.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 14, 2008
    Applicant: BENQ CORPORATION
    Inventors: Tzu-Huan Hsu, Chien-Ming Lee, Tsung-Hsun Wu
  • Patent number: 7289307
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: October 30, 2007
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ming Dou Ker, Chien Ming Lee
  • Publication number: 20070171587
    Abstract: The present invention provides ESD protection circuits. The circuit includes: a resistor, a capacitance, a first transistor, an inverter set, and a second transistor. The resistor is connected between a first voltage and node N1. The capacitor is connected between node N1 and a second voltage. The first transistor has a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and a third terminal coupled to node N2. The inverter set has an input terminal coupled to node N1 and an output terminal coupled to node N2. The second transistor has a first terminal coupled to a first inverter of the inverter set, a second terminal coupled to the second voltage, and a third terminal coupled to an output terminal of a second inverter of the inverter set. The output terminals of the first and the second inverters correspond to opposite logic levels.
    Type: Application
    Filed: January 26, 2006
    Publication date: July 26, 2007
    Inventors: Chien-Ming Lee, Ming-Dou Ker
  • Publication number: 20070126296
    Abstract: A stator structure includes a first cover, a stator assembly and a filler. The first cover has an accommodation space for accommodating the stator assembly therein. The filler is applied between the first cover and the stator assembly to surround the stator assembly. A manufacturing method of the stator structure is also disclosed.
    Type: Application
    Filed: April 20, 2006
    Publication date: June 7, 2007
    Inventors: Chien-Ming Lee, Deng-Chu Fu, Ying-Chi Chen, Wen-Shi Huang
  • Publication number: 20070103825
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 10, 2007
    Applicant: Silicon Integrated Systems Corp.
    Inventors: Ming-Dou Ker, Chien-Ming Lee
  • Publication number: 20070085426
    Abstract: A stator structure includes a stator assembly and a protective body, and the stator assembly is covered by the protective body. Additionally, a manufacturing method of the stator structure, which includes the steps of providing a stator assembly, providing a mold, disposing the stator assembly in the mold, applying a filler into a space defined between the mold and the stator assembly, and removing the mold to form the stator structure with the protective body, is also disclosed.
    Type: Application
    Filed: March 16, 2006
    Publication date: April 19, 2007
    Inventors: Chien-Ming Lee, Ying-Chi Chen, Wen-Shi Huang
  • Publication number: 20070030610
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit, and a trigger current generator. The object of the stacked MOS circuit is to be the first releasing path of the ESD current; the object of the trigger current generator is to generate the trigger current to turn on the stacked MOS circuit, and then the stacked MOS circuit would be the first releasing path of the ESD current.
    Type: Application
    Filed: November 17, 2005
    Publication date: February 8, 2007
    Applicant: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Ming-Dou Ker, Chien-Ming Lee
  • Publication number: 20070013290
    Abstract: An electrostatic discharge (ESD) circuitry bus within closed ring is disclosed. The closed ring comprises a plurality of metal layer. A metal layer can conduct electricity to another metal layer by conductive plugs. An oxide region can separate the closed ring into two closed ring regions by payout. Each closed ring region does not conduct electricity to each other by an oxide region. One closed ring section is Vdd bus. Therefore, the closed ring of the present invention can be sued by Vss bus and Vdd bus at the same time.
    Type: Application
    Filed: January 13, 2006
    Publication date: January 18, 2007
    Inventors: Ming-Dou Ker, Chien-Ming Lee
  • Patent number: 7096731
    Abstract: A gripping force measuring device includes a housing having a pressure detecting device and having a handle portion for being held by a user, a trigger attached to the housing and engaged with the pressure detecting device for applying a pressing force against the pressure detecting device when the trigger is forced toward the pressure detecting device. A displayer may be used for displaying the pressing force applied against the pressure detecting device. The trigger includes an arm having a free end extended out of the housing, and a lever is attached to the housing and includes a free end extended out of the housing for allowing the arm to be gripped and forced toward the lever.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: August 29, 2006
    Inventor: Mike Chien Ming Lee
  • Patent number: 6725728
    Abstract: A testing device includes a bladder coupled to a pressure gauge, for being squeezed or compressed by users to force air to the pressure gauge, and to measure gripping force of the users. A pumping device may be coupled to the bladder for pumping the bladder to the required pressure. A valve may be coupled between the pumping device and the bladder to control the pumping device. Two pivotal casings may be attached onto the bladder for pressing the bladder, and have flaps to be forced toward each other against the bladder.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: April 27, 2004
    Inventor: Mike Chien Ming Lee
  • Patent number: 6410117
    Abstract: The present invention discloses a rewritable phase-change optical disk having a recording material of a five-element alloy, Te—(Ge,Bi,Sb)—X, wherein X is B (boron) or C (carbon); Te (tellurium) ranges from 47 to 60 atomic percentage (at. %); Ge (germanium) ranges from 12 to 48 at. %; and Si (silicon) together with Sb (antimony) range from 5 to 41 at. %, based on the total atomic number of Te, Ge, Bi and Sb; and B or C range from 0.05 to 4 at. %, based on the total atomic number of Te, Ge, Bi, Sb and X.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 25, 2002
    Assignee: National Science Council
    Inventors: Tsung-Shune Chin, Chien-Ming Lee
  • Publication number: 20020041947
    Abstract: The present invention discloses a rewritable phase-change optical disk having a recording material of a five-element alloy, Te—(Ge,Bi,Sb)—X, wherein X is B (boron) or C (carbon); Te (tellurium) ranges from 47 to 60 atomic percentage (at. %); Ge (germanium) ranges from 12 to 48 at. %; and Si (silicon) together with Sb (antimony) range from 5 to 41 at. %, based on the total atomic number of Te, Ge, Bi and Sb; and B or C range from 0.05 to 4 at. %, based on the total atomic number of Te, Ge, Bi, Sb and X.
    Type: Application
    Filed: December 27, 2000
    Publication date: April 11, 2002
    Inventors: Tsung-Shune Chin, Chien-Ming Lee