Patents by Inventor Chien-Ming Lu

Chien-Ming Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240100553
    Abstract: A sprayer, comprising: a container, configured to contain liquid; a passage, comprising a first opening, a second opening, a resonator and a mesh, when the liquid is passed through the resonator, the liquid is emitted as a gas; a first optical sensor, configured to sense first optical data of at least portion of the mesh or at least portion of a surface of the container; and a processing circuit, configured to compute a foaming level of the mesh or of the surface according to the first optical data, and configured to determine whether the resonator should be turned off or not according to the foaming level. In another aspect, the processing circuit estimates a liquid level of the liquid but does not correspondingly turn off the resonator. By this way, the resonator may be turned on or turned off more properly and the liquid level may be more precisely estimated.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Applicant: PixArt Imaging Inc.
    Inventors: Shih-Jen Lu, Yang-Ming Chou, Chih-Hao Wang, Chien-Yi Kao, Hsin-Yi Lin
  • Publication number: 20240092662
    Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 21, 2024
    Inventors: Chien-Yen CHEN, Yi-Hsun HUANG, Pin-Yun LIN, Anggraeni Kumala DEWI, Koyeli DAS, Uttara SUKUL, Tsung-Hsien CHEN, Raju Kumar SHARMA, Cheng-Kang LU, Chung-Ming LU
  • Patent number: 11882683
    Abstract: A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 23, 2024
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ming Lu, Fu-Che Lee, Chien-Cheng Tsai, Chiu-Fang Hsu
  • Patent number: 11632887
    Abstract: A semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 18, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ming Lu, Fu-Che Lee, Feng-Yi Chang
  • Publication number: 20230067536
    Abstract: A semiconductor memory structure includes a substrate, a bit line disposed on the substrate, a dielectric liner disposed on a side of the bit line, and a capacitor contact and a filler disposed on the substrate. The bit line extends in a first direction. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. In a second direction perpendicular to the first direction, the capacitor contact is spaced apart from the bit line by the first nitride liner, the oxide liner, and the second nitride liner, and the width of the filler is greater than the width of the capacitor contact. A method for forming the semiconductor memory structure is also provided.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 2, 2023
    Inventors: Chien-Ming LU, Po-Han WU
  • Publication number: 20220122988
    Abstract: A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ming Lu, Fu-Che Lee, Chien-Cheng Tsai, Chiu-Fang Hsu
  • Publication number: 20210193665
    Abstract: A semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 24, 2021
    Inventors: Chien-Ming Lu, Fu-Che Lee, Feng-Yi Chang
  • Patent number: 10971498
    Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 6, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ming Lu, Fu-Che Lee, Feng-Yi Chang
  • Publication number: 20200066728
    Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.
    Type: Application
    Filed: September 20, 2018
    Publication date: February 27, 2020
    Inventors: Chien-Ming Lu, Fu-Che Lee, Feng-Yi Chang
  • Publication number: 20180286868
    Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.
    Type: Application
    Filed: March 2, 2018
    Publication date: October 4, 2018
    Inventors: Chien-Ming Lu, Fu-Che Lee, Chien-Cheng Tsai, Chiu-Fang Hsu
  • Publication number: 20160265755
    Abstract: An adjustable light bracket has a base, a track unit, and a power base. The base has a sliding base, a leading bolt, a leading nut, and a top board. The sliding base has a through hole. The leading bolt is mounted in the through hole and has a bottom abutting plate. The leading nut is mounted around the leading bolt by threads, is located in the through hole, is engaged in the through hole by a peripheral direction of the leading nut, and is moveable along the leading bolt in the through hole. The top board is mounted on the sliding base. The leading nut is limited between the bottom abutting plate and the top board. The sliding base is mounted in the track unit. The power base is mounted in the track unit and located at a position opposite the base.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 15, 2016
    Inventor: Chien-Ming LU
  • Patent number: 9247819
    Abstract: A tube fixing device has an outer tube, an inner tube, two fixing pins, and a fixing stick. The outer tube has an aligning hole formed through the outer tube. The inner tube is rotatably inserted into the outer tube and has two tapered fixing recesses formed in the inner tube and selectively aligned with the aligning hole. The fixing pins are combined with the inner tube and abut the outer tube at different locations according to the rotation of the inner tube relative to the outer tube. The fixing stick is retractably combined with the outer tube and has a stick tube and a tapered insertion stick inserted in one of the fixing recesses. The insertion end, the fixing pins and the inner tube selectively form a three-point contact status.
    Type: Grant
    Filed: September 14, 2013
    Date of Patent: February 2, 2016
    Inventor: Chien-Ming Lu
  • Publication number: 20150076292
    Abstract: A tube fixing device has an outer tube, an inner tube, two fixing pins, and a fixing stick. The outer tube has an aligning hole formed through the outer tube. The inner tube is rotatably inserted into the outer tube and has two tapered fixing troughs formed in the inner tube and selectively aligned with the aligning hole. The fixing pins are combined with the inner tube and abut the outer tube at different locations according to the rotation of the inner tube relative to the outer tube. The fixing stick is retractably combined with the outer tube and has a stick tube and a tapered insertion stick inserted in one of the fixing troughs. The insertion end, the fixing pins and the inner tube selectively form a three-point contact status.
    Type: Application
    Filed: September 14, 2013
    Publication date: March 19, 2015
    Inventor: Chien-Ming LU
  • Publication number: 20130201404
    Abstract: An image processing method of an image processing apparatus includes: determining static pixels and non-static pixels of a current image frame; dividing the current image frame into a plurality of blocks, wherein each block comprises a plurality of pixels; determining static blocks and non-static blocks of the current image frame by referring to at least the static pixels and the non-static pixels of the current image frame; and refining determination of the static pixels and the non-static pixels of the current image frame according to the static blocks and the non-static blocks.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Inventors: Chien-Ming Lu, Yin-Ho Su, Chien-Chang Lin
  • Publication number: 20100239384
    Abstract: A molly bolt has a fastener, a sleeve and a tip. The fastener has a head and a shaft. The shaft is formed on and protrudes from the head and has a threaded segment. The sleeve is mounted around the shaft and has a fixing end, a rim, a compressing segment and an asymmetric structure. The fixing end is disposed adjacent to the head. The rim is formed around the fixing end. The compressing segment is formed from and protrudes from the fixing end. The asymmetric structure is a slot or multiple asymmetric slots respectively formed in the compressing segment. The tip is mounted on the connecting end of the fastener. The asymmetric structure causes asymmetric deformation preventing the molly bolt from loosening.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 23, 2010
    Inventor: Chien-Ming LU
  • Publication number: 20080008554
    Abstract: A self-drilling wall anchor device has a central bolt, an outer sleeve and a drilling head. The central bolt has a bolt body, a head, a connection portion and an engaging portion. The outer sleeve is mounted around the bolt body of the central bolt and has a flange, a second thread, a compressed head and a deformable portion. The compressed head is formed on the distal end of the outer sleeve and has a through hole. The through hole is defined through the compressed head and engages with the engaging portion on the central bolt.
    Type: Application
    Filed: September 19, 2007
    Publication date: January 10, 2008
    Inventor: Chien-Ming Lu
  • Publication number: 20060228188
    Abstract: A self-drilling wall anchor device has a central bolt, an outer sleeve and a drilling head. The central bolt has a bolt body, a head and a connection portion. The bolt body has a first thread formed around the bolt body. The outer sleeve is mounted around the bolt body of the central bolt and has a flange, a second thread, a compressed head and a deformable portion. The flange is radially formed on and extends from the proximal end of the outer sleeve. The second thread is formed around the outer sleeve near the flange. The compressed head is formed on the distal end of the outer sleeve and has a through hole. The through hole is defined through the compressed head and has a diameter larger than that of the connection portion and smaller than that of the first thread.
    Type: Application
    Filed: June 7, 2006
    Publication date: October 12, 2006
    Inventors: Chin-Jen Hsu, Ming-Chia Cheng, Chien-Ming Lu