Patents by Inventor Chien-Mo Li
Chien-Mo Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11500018Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: GrantFiled: June 25, 2021Date of Patent: November 15, 2022Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ting-Yu Shen, Chien-Mo Li
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Publication number: 20210325458Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Ting-Yu Shen, Chien-Mo Li
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Patent number: 11073552Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: GrantFiled: September 30, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Patent number: 11047911Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: GrantFiled: August 14, 2019Date of Patent: June 29, 2021Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ting-Yu Shen, Chien-Mo Li
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Publication number: 20200132759Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: ApplicationFiled: August 14, 2019Publication date: April 30, 2020Inventors: Ting-Yu Shen, Chien-Mo Li
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Publication number: 20200025826Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Patent number: 10429440Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: GrantFiled: July 26, 2017Date of Patent: October 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Publication number: 20190033366Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Patent number: 9983264Abstract: A multiple defect diagnosis method includes: receiving a gate-level netlist of a chip, a plurality of test patterns and a plurality of test failure reports; deriving a plurality of seed nets from the gate-level netlist according to the plurality of test patterns and the plurality of test failure reports; utilizing a processor to compute similarity between the plurality of seed nets, and accordingly merging the plurality of seed nets to obtain a single seed net tree; and deriving at least one suspected seed net according to the single seed net tree.Type: GrantFiled: October 20, 2014Date of Patent: May 29, 2018Assignee: Realtek Semiconductor Corp.Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Chieh-Chih Che
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Patent number: 9213799Abstract: A systematic defect analyzing method, includes: partitioning physical sites into groups to obtain a plurality of groups of physical sites according to a plurality of physical features of a chip corresponding to different potential systematic defects; utilizing a processor to compute at least one defect probability of each group of physical sites; and deriving an analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of physical sites.Type: GrantFiled: August 13, 2014Date of Patent: December 15, 2015Assignee: Realtek Semiconductor Corp.Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Po-Juei Chen
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Publication number: 20150204939Abstract: A multiple defect diagnosis method includes: receiving a gate-level netlist of a chip, a plurality of test patterns and a plurality of test failure reports; deriving a plurality of seed nets from the gate-level netlist according to the plurality of test patterns and the plurality of test failure reports; utilizing a processor to compute similarity between the plurality of seed nets, and accordingly merging the plurality of seed nets to obtain a single seed net tree; and deriving at least one suspected seed net according to the single seed net tree.Type: ApplicationFiled: October 20, 2014Publication date: July 23, 2015Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Chieh-Chih Che
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Publication number: 20150205907Abstract: A systematic defect analyzing method, includes: partitioning physical sites into groups to obtain a plurality of groups of physical sites according to a plurality of physical features of a chip corresponding to different potential systematic defects; utilizing a processor to compute at least one defect probability of each group of physical sites; and deriving an analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of physical sites.Type: ApplicationFiled: August 13, 2014Publication date: July 23, 2015Inventors: Pei-Ying Hsueh, Chun-Yi Kuo, Chien-Mo Li, Po-Juei Chen
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Patent number: 8468407Abstract: In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.Type: GrantFiled: August 19, 2011Date of Patent: June 18, 2013Assignees: Global Unichip Corp., National Taiwan University, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Jen-Yang Wen, Chien-Mo Li
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Publication number: 20120233513Abstract: In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.Type: ApplicationFiled: August 19, 2011Publication date: September 13, 2012Inventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Jen-Yang Wen, Chien-Mo Li
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Publication number: 20100185909Abstract: Disclosed is a dual-rail asynchronous insensitive scan chain circuit designed for test. This scan chain does not require any clock even in scan mode, so it is truly an asynchronous design for testability. The normal function of the asynchronous scan chain can not be affected when removing any clock controls. The handshake protocols between two sequential elements used in the asynchronous scan chain become the scan chain transmission structure, rather than the timing control used in synchronous scan chain in the prior arts. Therefore, both in the function mode and scan mode, the scan chain always operates under the asynchronous condition. It not only can reach a complete test scanning, achieve high fault detection coverage and consume lower power, but also avoid the clock skew problem.Type: ApplicationFiled: January 4, 2010Publication date: July 22, 2010Applicant: National Taiwan UniversityInventors: Chien-Mo Li, Chi-Hsuan Cheng