Patents by Inventor Chien-Ning YAO
Chien-Ning YAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12211922Abstract: Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.Type: GrantFiled: July 19, 2023Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
-
Patent number: 12205998Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.Type: GrantFiled: January 14, 2022Date of Patent: January 21, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien-Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
-
Patent number: 12166129Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a nanostructure over the fin. The semiconductor device structure includes a gate stack wrapping around an upper portion of the fin and the nanostructure. The semiconductor device structure includes an inner spacer between the fin and the nanostructure. The semiconductor device structure includes a film in the inner spacer. A first dielectric constant of the film is lower than a second dielectric constant of the inner spacer. The semiconductor device structure includes a low dielectric constant structure in the film.Type: GrantFiled: April 21, 2023Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Chi-On Chui, Chien-Ning Yao
-
Publication number: 20240395859Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Inventors: Zhi-Chang LIN, Chien Ning YAO, Shih-Cheng CHEN, Jung-Hung CHANG, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
-
Publication number: 20240387738Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
-
Publication number: 20240379875Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dummy gate structure over the first fin structure and the second fin structure, and removing a portion of the first fin structure and the second fin structure to form a first source/drain (S/D) recess and a second S/D recess. The method includes forming a first bottom layer in the first S/D recess and a second bottom layer in the second S/D recess, and forming a first dielectric liner layer over the first bottom layer. The method includes forming a first top layer over the first dielectric liner layer, and forming a first S/D structure over the first top layer and a second S/D structure over the second bottom layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien-Ning YAO, Tsung-Han CHUANG, Kai-Lin CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
-
Publication number: 20240379855Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
-
Publication number: 20240372010Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chien Ning Yao, Chi On Chui
-
Publication number: 20240363703Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung CHANG, Lo Heng CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien-Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
-
Publication number: 20240355908Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.Type: ApplicationFiled: June 28, 2024Publication date: October 24, 2024Inventors: Tsung-Han CHUANG, Zhi-Chang LIN, Shih-Cheng CHEN, Jung-Hung CHANG, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
-
Publication number: 20240355901Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.Type: ApplicationFiled: April 18, 2023Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Chih-Hao WANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Zhi-Chang LIN, Chien-Ning YAO, Tsung-Han CHUANG
-
Publication number: 20240355907Abstract: A device includes: a stack of semiconductor channels; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; a source/drain contact on the source/drain region; and a gate spacer between the source/drain contact and the gate structure. The gate spacer includes: a first spacer layer in contact with the gate structure; and a second spacer layer between the first spacer layer and the source/drain contact, the second spacer layer having a first portion on the stack and a second portion on the first portion, the second portion being thinner than the first portion.Type: ApplicationFiled: August 25, 2023Publication date: October 24, 2024Inventors: Shih-Cheng CHEN, Jung-Hung CHANG, Chien Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
-
Patent number: 12125922Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.Type: GrantFiled: July 24, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chien Ning Yao, Chi On Chui
-
Patent number: 12107169Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.Type: GrantFiled: July 10, 2023Date of Patent: October 1, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
-
Publication number: 20240313082Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap extending in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.Type: ApplicationFiled: May 20, 2024Publication date: September 19, 2024Inventors: Chien Ning Yao, Bo-Feng Young, Chih-Hao Wang, Kuan-Lun Cheng, Sai-Hooi Yeong
-
Publication number: 20240304687Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.Type: ApplicationFiled: August 11, 2023Publication date: September 12, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien Ning Yao, Chia-Hao Chang, Shih-Cheng Chen, Chih-Hao Wang, Chia-Cheng Tsai, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Tsung-Han Chuang
-
Patent number: 12074204Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.Type: GrantFiled: July 23, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Hung Chang, Lo Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
-
Patent number: 12051736Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.Type: GrantFiled: August 31, 2021Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
-
Publication number: 20240234419Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: ApplicationFiled: March 22, 2024Publication date: July 11, 2024Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Lo Heng CHANG, CHIH-HAO WANG, Chien Ning YAO, Kuo-Cheng CHIANG
-
Publication number: 20240194758Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.Type: ApplicationFiled: February 22, 2024Publication date: June 13, 2024Inventors: Zhi-Chang LIN, Kuan-Ting PAN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO, Kuo-Cheng CHIANG