Patents by Inventor Chien-Pang Lu
Chien-Pang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10848178Abstract: A compressor, an adder circuit, and an operation method thereof are provided. The compressor includes a first adder circuit and a second adder circuit. The first adder circuit receives a plurality of input values. The first adder circuit outputs a first inverted sum value (an inverted signal of a sum value) and a first inverted carry value (an inverted signal of a carry value). One of a plurality of input terminals of the second adder circuit is coupled to the first adder circuit to receive one of the first inverted sum value and the first inverted carry value. The second adder circuit outputs a second inverted sum value and a second inverted carry value.Type: GrantFiled: June 22, 2020Date of Patent: November 24, 2020Assignee: DigWise Technology Corporation, LTDInventors: JingJie Wu, Chih-Wen Yang, Shih-Che Yen, Chien-Pang Lu
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Patent number: 10498339Abstract: Methods and apparatuses pertaining to hold-time compensation using free metal segments or other electrically-conductive segments of an IC are described. An integrated circuit (IC) having free segment hold-time compensation may include a monolithic semiconductor substrate which has a first device and a second device disposed thereon. In addition, the IC may include an electrical node electrically connecting the first and second devices. The electrical node may include one or more electrically-conductive elements that contribute to a total capacitance at the electrical node such that the total capacitance at the electrical node has a value that fulfills a hold-time requirement at the electrical node.Type: GrantFiled: March 13, 2018Date of Patent: December 3, 2019Assignee: MEDIATEK INC.Inventors: Chien-Pang Lu, Yu-Tung Chang, Yu-Ming Yang
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Publication number: 20180278253Abstract: Methods and apparatuses pertaining to hold-time compensation using free metal segments or other electrically-conductive segments of an IC are described. An integrated circuit (IC) having free segment hold-time compensation may include a monolithic semiconductor substrate which has a first device and a second device disposed thereon. In addition, the IC may include an electrical node electrically connecting the first and second devices. The electrical node may include one or more electrically-conductive elements that contribute to a total capacitance at the electrical node such that the total capacitance at the electrical node has a value that fulfills a hold-time requirement at the electrical node.Type: ApplicationFiled: March 13, 2018Publication date: September 27, 2018Inventors: Chien-Pang Lu, Yu-Tung Chang, Yu-Ming Yang
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Patent number: 9805155Abstract: A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.Type: GrantFiled: January 28, 2016Date of Patent: October 31, 2017Assignee: MEDIATEK INC.Inventors: Chien-Pang Lu, Yu-Tung Chang
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Patent number: 9484134Abstract: A feedthrough signal transmission circuit includes a first permanently on cell and a cell controlling unit. The first permanently on cell is arranged to transmit a first control signal. The cell controlling unit is coupled to the first permanently on cell, and includes a power switch and a plurality o buffers. The power switch is coupled to the first permanently on cell, arranged to receive a switch control signal and the first control signal, and selectively output the first control signal according to the switch control signal. The plurality of buffers is coupled to the power switch. Each of the buffers is arranged to buffer a data input only when powered by the first control signal output from the power switch.Type: GrantFiled: March 26, 2014Date of Patent: November 1, 2016Assignee: MEDIATEK INC.Inventors: Chien-Pang Lu, Yu-Tung Chang
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Publication number: 20160292340Abstract: A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.Type: ApplicationFiled: January 28, 2016Publication date: October 6, 2016Inventors: Chien-Pang LU, Yu-Tung CHANG
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Publication number: 20160248423Abstract: A feedthrough signal transmission apparatus, fabricated on a single silicon, includes a plurality of feedthrough signal transmission circuits and a permanently on control cell that is coupled to the feedthrough signal transmission circuits, where each feedthrough signal transmission circuit of the feedthrough signal transmission circuits may include at least one sub-circuit that is kept in a power on state when the sub-circuit performs feedthrough signal transmission. For example, and the sub-circuit may include a permanently on-for-feedthrough repeater (e.g. a repeater that is kept in the power on state when the repeater performs feedthrough signal transmission). In addition, the permanently on control cell may be configured to maintain the power on state of the sub-circuit when the sub-circuit performs feedthrough signal transmission. For example, sub-circuits of the feedthrough signal transmission circuits are located at grid-based locations, respectively.Type: ApplicationFiled: May 3, 2016Publication date: August 25, 2016Inventors: Chien-Pang Lu, Yu-Tung Chang
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Publication number: 20150279522Abstract: A feedthrough signal transmission circuit includes a first permanently on cell and a cell controlling unit. The first permanently on cell is arranged to transmit a first control signal. The cell controlling unit is coupled to the first permanently on cell, and includes a power switch and a plurality o buffers. The power switch is coupled to the first permanently on cell, arranged to receive a switch control signal and the first control signal, and selectively output the first control signal according to the switch control signal. The plurality of buffers is coupled to the power switch. Each of the buffers is arranged to buffer a data input only when powered by the first control signal output from the power switch.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Applicant: MEDIATEK INC.Inventors: Chien-Pang Lu, Yu-Tung Chang
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Patent number: 8898050Abstract: A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor.Type: GrantFiled: November 30, 2010Date of Patent: November 25, 2014Assignee: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Patent number: 8479137Abstract: A congestive placement preventing apparatus for modifying a circuit layout includes an analyzing module, a defining module and an extension module. The analyzing module performs a congestion analysis on the circuit layout to generate an analysis result. The defining module defines a congestion region and a share region adjacent to the congestion region on the circuit layout according to the analysis result. A density of electronic cells of the congestion region is higher than that of electronic cells of the share region. The extension module arranges a plurality of electronic cells in the congestion region to the congestion region and the share region, thereby reducing the density of electronic cells in the congestion region.Type: GrantFiled: March 4, 2011Date of Patent: July 2, 2013Assignee: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Patent number: 8370788Abstract: A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic circuit, so that a plurality of comparing points are generated in an APR gate level HDL of the logic circuit. Then the method performs a backward functional equivalent check on the APR gate level HDL of the logic circuit to find a change point according to the comparing points.Type: GrantFiled: February 2, 2010Date of Patent: February 5, 2013Assignee: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Patent number: 8250512Abstract: A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule.Type: GrantFiled: November 24, 2010Date of Patent: August 21, 2012Assignee: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Patent number: 8141023Abstract: A congestive placement preventing apparatus, applied in a logic circuit layout having 2K logic circuits, where K is a positive integer, is provided. The congestive placement preventing apparatus includes a restructuring module and a synthesizing module. The restructuring module adds a selecting unit in the logic circuit layout, and adds (N?K) buffers in each of the 2K logic circuits, where N is a positive integer. The synthesizing module synthesizes the restructured logic circuit layout according to a plurality of “don't touch” synthesizing commands associated with the added buffers. In the synthesized logic circuit layout, all of the 2K logic circuits are independent and not coupled or merged with one another.Type: GrantFiled: July 13, 2009Date of Patent: March 20, 2012Assignee: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Patent number: 8056041Abstract: An apparatus of preventing congestive placement is provided. The apparatus comprises a judging module, a pattern generating module, and a placement module. The judging module judges whether a circuit layout comprises a congestive region according to a judging rule. When a judgment result of the judging module is affirmative, the pattern generating module generates a redistribution pattern with a density distribution of blockages. The density distribution gradually decreases outward. The placement module regards the congestive region as the center redistributes the blockages and electronic cells according to the redistribution pattern.Type: GrantFiled: May 25, 2009Date of Patent: November 8, 2011Assignee: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Publication number: 20110219346Abstract: A congestive placement preventing apparatus for modifying a circuit layout includes an analyzing module, a defining module and an extension module. The analyzing module performs a congestion analysis on the circuit layout to generate an analysis result. The defining module defines a congestion region and a share region adjacent to the congestion region on the circuit layout according to the analysis result. A density of electronic cells of the congestion region is higher than that of electronic cells of the share region. The extension module arranges a plurality of electronic cells in the congestion region to the congestion region and the share region, thereby reducing the density of electronic cells in the congestion region.Type: ApplicationFiled: March 4, 2011Publication date: September 8, 2011Applicant: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Publication number: 20110153303Abstract: A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor.Type: ApplicationFiled: November 30, 2010Publication date: June 23, 2011Applicant: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Publication number: 20110126166Abstract: A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule.Type: ApplicationFiled: November 24, 2010Publication date: May 26, 2011Applicant: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Publication number: 20100281443Abstract: A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic circuit, so that a plurality of comparing points are generated in an APR gate level HDL of the logic circuit. Then the method performs a backward functional equivalent check on the APR gate level HDL of the logic circuit to find a change point according to the comparing points.Type: ApplicationFiled: February 2, 2010Publication date: November 4, 2010Applicant: MStar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu
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Publication number: 20100271066Abstract: A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip.Type: ApplicationFiled: June 10, 2009Publication date: October 28, 2010Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: CHEN-HSING LO, CHIEN-PANG LU
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Patent number: 7821288Abstract: A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip.Type: GrantFiled: June 10, 2009Date of Patent: October 26, 2010Assignee: Mstar Semiconductor, Inc.Inventors: Chen-Hsing Lo, Chien-Pang Lu