Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: A memory access apparatus is coupled to a memory unit and includes a header access circuit and a payload access circuit. The header access circuit includes a header fetching unit used to fetch a header descriptor in the memory unit, and the payload access circuit includes a payload fetching unit used to fetch a payload descriptor in the memory unit. The header access circuit and the payload access circuit perform fetching with respect to the memory unit in a non-sequenced manner.