Abstract: A surface-emitting laser including a cladding layer, an active region, a first grating, a plurality of second gratings, a first electrode, and a second electrode is provided. The active region is disposed on the cladding layer. The first grating is disposed on the active region. The second gratings are disposed on the active region and separately distributed among the first grating. A diffraction order of the first grating is different from a diffraction order of the second gratings. The first electrode is electrically connected to the cladding layer. The second electrode covers at least the first grating.

Abstract: Methods for cleaning integrated circuit (IC) wafers after undergoing planarization processes (for example, chemical mechanical polishing processes) and associated cleaning units and/or planarization units are disclosed herein. An exemplary method includes configuring outlet areas of spray nozzles to deliver a cleaning solution to optimal locations of the IC wafer and delivering the cleaning solution via the spray nozzles having the configured outlet areas to the IC wafer. Each of the outlet areas is configured to achieve a particular velocity of the cleaning solution exiting the outlet area, such that the cleaning solution reaches a particular location of the IC wafer depending on the particular velocity. In some implementations, the cleaning solution enters inlet areas of the spray nozzles at the same flow rate and the cleaning solution exits the outlet areas of the spray nozzles at different velocities.

Abstract: Methods for cleaning integrated circuit (IC) wafers after undergoing planarization processes (for example, chemical mechanical polishing processes) and associated cleaning units and/or planarization units are disclosed herein. An exemplary method includes configuring outlet areas of spray nozzles to deliver a cleaning solution to optimal locations of the IC wafer and delivering the cleaning solution via the spray nozzles having the configured outlet areas to the IC wafer. Each of the outlet areas is configured to achieve a particular velocity of the cleaning solution exiting the outlet area, such that the cleaning solution reaches a particular location of the IC wafer depending on the particular velocity. In some implementations, the cleaning solution enters inlet areas of the spray nozzles at the same flow rate and the cleaning solution exits the outlet areas of the spray nozzles at different velocities.

Abstract: The present disclosure provides a cleaning unit for a chemical mechanical polishing (CMP) process. The cleaning unit comprises a cleaning solution; a brush configured to scrub a wafer during the CMP process; and a spray nozzle configured to apply the cleaning solution to the wafer when the brush scrubs the wafer during the CMP process. In some embodiments, the spray nozzle includes an inlet where the cleaning solution enters the spray nozzle and an outlet where the cleaning solution exits the spray nozzle. In some embodiments, an inlet area (A0) is different from an outlet area (A1).

Abstract: Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization on an article includes a polishing head configured to perform a chemical-mechanical planarization (CMP) on an article, a polishing pad configured to support the article, a light source configured to emit an incident light, a polishing fluid including a plurality of emitter particles capable of emitting a fluorescent light in response to the incident light, a fluorescence light detector configured to detect the fluorescent light, and at least one processor configured to control the polishing head based on the detected fluorescent light.

Abstract: Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization on an article includes a polishing head configured to perform a chemical-mechanical planarization (CMP) on an article, a polishing pad configured to support the article, a light source configured to emit an incident light, a polishing fluid including a plurality of emitter particles capable of emitting a fluorescent light in response to the incident light, a fluorescence light detector configured to detect the fluorescent light, and at least one processor configured to control the polishing head based on the detected fluorescent light.

Abstract: The present disclosure provides a cleaning unit for a chemical mechanical polishing (CMP) process. The cleaning unit comprises a cleaning solution; a brush configured to scrub a wafer during the CMP process; and a spray nozzle configured to apply the cleaning solution to the wafer when the brush scrubs the wafer during the CMP process. In some embodiments, the spray nozzle includes an inlet where the cleaning solution enters the spray nozzle and an outlet where the cleaning solution exits the spray nozzle. In some embodiments, an inlet area (A0) is different from an outlet area (A1).

Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.

Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device comprises a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer comprises multiple quantum dot layers.

Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

Abstract: The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.

Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (continuous or stepped) doping between the base region and the underlying subcollector region with the collector doping being lowest near the base and highest near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

Abstract: The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.

Abstract: A method of fabricating quantum dot structures and devices including the steps of: (i) forming a quantum well membrane on a substrate; (ii) on the quantum well membrane forming a masking layer including a plurality of dot-shaped mask regions which protect the underlying quantum well membrane; (iii) using thermal etching to evaporate portions of the quantum well membrane that are not protected by the dotted mask regions of the masking layer so as to form a plurality of quantum dots; and (iv) after thermal etching, covering the plurality of quantum dots with a layer of material having an energy gap that is greater than the energy gap of the quantum well membrane. The quantum dot produced by this invention is found to generate ten times more illumination than the prior art when measured by photoluminescence.

Abstract: A method is disclosed which is capable of producing improved field effect transistors such as high electron mobility transistors and metal semiconductor field effect transistors. The method comprises a dual level photoresist deposition technique on a semiconductor wafer, in conjunction with a double lift-off and dummy gate procedure. In the process, T-bar shaped portions of overlying top and bottom photoresist layers are produced, one of such T-bar shaped portions forming a dummy gate. Metal is then deposited on the upper surface of the T-bar shaped portions and on the exposed surface of the substrate to form a source and a drain. In a first lift-off step the metal on the T-bar shaped portions and the underlying remaining top layer portions, are removed. An inorganic film such as SiO is then deposited on the remaining bottom layer portions and over the metal on the surface of the substrate.

Abstract: A metal-semiconductor field-effect transistor (MESFET) is provided with a p-type region adjacent the n-type region under the drain contact. Holes injected from this p-type region compensate the negative space charge region at the channel to substrate interface, thus minimizing considerable substrate effects.

Abstract: A heterojunction-type laser is constructed with two closely spaced p-n junctions. Ohmic contacts are provided on both sides of the p-n junctions so that the voltages across the junctions can be individually controlled. By controlling the ratio of the voltages, the carrier distribution in the lasing active layer is controlled. This in turn controls the direction of the output beam of the laser in accordance with the ratio of the voltages, providing a laser beam which can be scanned without requiring mechanical means.

Abstract: Solid state electro-optical devices are formed on a semi-insulating substrate, with all contacts of each device being on the same side of the substrate. These devices include two types of lasers, one operating on current crowding effect and the other by lateral diffusions. Either type laser is integratable with an electronic device e.g. a Gunn oscillator or an FET on the common semi-insulating substrate to form a complex monolithic electro-optical device.

Abstract: Solid state electro-optical devices are formed on a semi-insulating substrate, with all contacts of each device being on the same side of the substrate. These devices include two types of lasers, one operating on current crowding effect and the other by lateral diffusions. Either type laser is integratable with an electronic device e.g. a Gunn oscillator or an FET on the common semi-insulating substrate to form a complex monolithic electro-optical device.