Patents by Inventor Chien-Ping Lee

Chien-Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404250
    Abstract: An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yu Wang, Hung-Bin Lin, Shih-Ping Hong, Shih-Hao Chen, Chen-Hsiang Lu, Ping-Chung Lee
  • Publication number: 20220238730
    Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yueh Ying LEE, Chien-Ying WU, Chia-Ping LAI
  • Publication number: 20220236894
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
  • Publication number: 20220224081
    Abstract: A surface-emitting laser including a cladding layer, an active region, a first grating, a plurality of second gratings, a first electrode, and a second electrode is provided. The active region is disposed on the cladding layer. The first grating is disposed on the active region. The second gratings are disposed on the active region and separately distributed among the first grating. A diffraction order of the first grating is different from a diffraction order of the second gratings. The first electrode is electrically connected to the cladding layer. The second electrode covers at least the first grating.
    Type: Application
    Filed: January 12, 2022
    Publication date: July 14, 2022
    Applicant: Phosertek Corporation
    Inventors: Chien-Ping Lee, Kuo-Jui Lin, Chien-Hung Lin, Bo-Tsun Chou
  • Patent number: 11387408
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 12, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20220216111
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11264232
    Abstract: Methods for cleaning integrated circuit (IC) wafers after undergoing planarization processes (for example, chemical mechanical polishing processes) and associated cleaning units and/or planarization units are disclosed herein. An exemplary method includes configuring outlet areas of spray nozzles to deliver a cleaning solution to optimal locations of the IC wafer and delivering the cleaning solution via the spray nozzles having the configured outlet areas to the IC wafer. Each of the outlet areas is configured to achieve a particular velocity of the cleaning solution exiting the outlet area, such that the cleaning solution reaches a particular location of the IC wafer depending on the particular velocity. In some implementations, the cleaning solution enters inlet areas of the spray nozzles at the same flow rate and the cleaning solution exits the outlet areas of the spray nozzles at different velocities.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chien-Ping Lee, Hui-Chi Huang
  • Publication number: 20180247838
    Abstract: Methods for cleaning integrated circuit (IC) wafers after undergoing planarization processes (for example, chemical mechanical polishing processes) and associated cleaning units and/or planarization units are disclosed herein. An exemplary method includes configuring outlet areas of spray nozzles to deliver a cleaning solution to optimal locations of the IC wafer and delivering the cleaning solution via the spray nozzles having the configured outlet areas to the IC wafer. Each of the outlet areas is configured to achieve a particular velocity of the cleaning solution exiting the outlet area, such that the cleaning solution reaches a particular location of the IC wafer depending on the particular velocity. In some implementations, the cleaning solution enters inlet areas of the spray nozzles at the same flow rate and the cleaning solution exits the outlet areas of the spray nozzles at different velocities.
    Type: Application
    Filed: May 1, 2018
    Publication date: August 30, 2018
    Inventors: Chien-Ping Lee, Hui-Chi Huang
  • Patent number: 9966281
    Abstract: The present disclosure provides a cleaning unit for a chemical mechanical polishing (CMP) process. The cleaning unit comprises a cleaning solution; a brush configured to scrub a wafer during the CMP process; and a spray nozzle configured to apply the cleaning solution to the wafer when the brush scrubs the wafer during the CMP process. In some embodiments, the spray nozzle includes an inlet where the cleaning solution enters the spray nozzle and an outlet where the cleaning solution exits the spray nozzle. In some embodiments, an inlet area (A0) is different from an outlet area (A1).
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Ping Lee, Hui-Chi Huang
  • Patent number: 9305851
    Abstract: Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization on an article includes a polishing head configured to perform a chemical-mechanical planarization (CMP) on an article, a polishing pad configured to support the article, a light source configured to emit an incident light, a polishing fluid including a plurality of emitter particles capable of emitting a fluorescent light in response to the incident light, a fluorescence light detector configured to detect the fluorescent light, and at least one processor configured to control the polishing head based on the detected fluorescent light.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Shuo Liu, Hui-Chi Huang, Jung-Tsan Tsai, Chien-Ping Lee
  • Publication number: 20150140818
    Abstract: The present disclosure provides a cleaning unit for a chemical mechanical polishing (CMP) process. The cleaning unit comprises a cleaning solution; a brush configured to scrub a wafer during the CMP process; and a spray nozzle configured to apply the cleaning solution to the wafer when the brush scrubs the wafer during the CMP process. In some embodiments, the spray nozzle includes an inlet where the cleaning solution enters the spray nozzle and an outlet where the cleaning solution exits the spray nozzle. In some embodiments, an inlet area (A0) is different from an outlet area (A1).
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Inventors: Chien-Ping Lee, Hui-Chi Huang
  • Publication number: 20150140691
    Abstract: Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization on an article includes a polishing head configured to perform a chemical-mechanical planarization (CMP) on an article, a polishing pad configured to support the article, a light source configured to emit an incident light, a polishing fluid including a plurality of emitter particles capable of emitting a fluorescent light in response to the incident light, a fluorescence light detector configured to detect the fluorescent light, and at least one processor configured to control the polishing head based on the detected fluorescent light.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-SHUO LIU, HUI-CHI HUANG, JUNG-TSAN TSAI, CHIEN-PING LEE
  • Patent number: 7977666
    Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: July 12, 2011
    Assignee: Academia Sinica
    Inventors: Shiang-Yu Wang, Hong-Shi Ling, Ming-Cheng Lo, Chien-Ping Lee
  • Publication number: 20100117060
    Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device comprises a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer comprises multiple quantum dot layers.
    Type: Application
    Filed: April 29, 2009
    Publication date: May 13, 2010
    Applicant: Academia Sinica
    Inventors: Shiang-Yu Wang, Hong-Shi Ling, Ming-Cheng Lo, Chien-Ping Lee
  • Patent number: 7012288
    Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: March 14, 2006
    Assignee: WJ Communications, Inc.
    Inventors: Chien Ping Lee, Hin Fai Chau, Nanlei Larry Wang, Clarence John Dunnrowicz, Yan Chen, Barry Jia-Fu Lin
  • Patent number: 6806513
    Abstract: The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: October 19, 2004
    Assignee: EIC Corporation
    Inventors: Hin Fai Chau, Clarence John Dunnrowicz, Yan Chen, Chien Ping Lee
  • Publication number: 20040188712
    Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (continuous or stepped) doping between the base region and the underlying subcollector region with the collector doping being lowest near the base and highest near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicant: EiC Corporation
    Inventors: Chien Ping Lee, Frank Hin Fai Chau, Nanlei Larry Wang, Clarence John Dunnrowicz, Yan Chen, Barry Jia-Fu Lin
  • Publication number: 20040065898
    Abstract: The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: EiC Corporation
    Inventors: Hin Fai Chau, Clarence John Dunnrowicz, Yan Chen, Chien Ping Lee
  • Publication number: 20040065897
    Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: EiC Corporation
    Inventors: Chien Ping Lee, Hin Fai Chau, Nanlei Larry Wang, Clarence John Dunnrowicz, Yan Chen, Barry Jia-Fu Lin
  • Patent number: 5482890
    Abstract: A method of fabricating quantum dot structures and devices including the steps of: (i) forming a quantum well membrane on a substrate; (ii) on the quantum well membrane forming a masking layer including a plurality of dot-shaped mask regions which protect the underlying quantum well membrane; (iii) using thermal etching to evaporate portions of the quantum well membrane that are not protected by the dotted mask regions of the masking layer so as to form a plurality of quantum dots; and (iv) after thermal etching, covering the plurality of quantum dots with a layer of material having an energy gap that is greater than the energy gap of the quantum well membrane. The quantum dot produced by this invention is found to generate ten times more illumination than the prior art when measured by photoluminescence.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: January 9, 1996
    Assignee: National Science Council
    Inventors: Der-Cherng Liu, Chien-Ping Lee