Patents by Inventor Chien-Ping Lu
Chien-Ping Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11940659Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
-
Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
-
Patent number: 10223334Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix multiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: July 20, 2017Date of Patent: March 5, 2019Assignee: NOVUMIND LIMITEDInventors: Chien-Ping Lu, Yu-Shuen Tang
-
Patent number: 10216704Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix multiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: July 20, 2017Date of Patent: February 26, 2019Assignee: NOVUMIND LIMITEDInventors: Chien-Ping Lu, Yu-Shuen Tang
-
Patent number: 10169298Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix multiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: May 11, 2017Date of Patent: January 1, 2019Assignee: NOVUMIND LIMITEDInventors: Chien-Ping Lu, Yu-Shuen Tang
-
Patent number: 10073816Abstract: A native tensor processor calculates tensor contractions using a sum of outer products. In one implementation, the native tensor processor preferably is implemented as a single integrated circuit and includes an input buffer and a contraction engine. The input buffer buffers tensor elements retrieved from off-chip and transmits the elements to the contraction engine as needed. The contraction engine calculates the tensor contraction by executing calculations from an equivalent matrix multiplications, as if the tensors were unfolded into matrices, but avoiding the overhead of expressly unfolding the tensors. The contraction engine includes a plurality of outer product units that calculate matrix mutiplications by a sum of outer products. By using outer products, the equivalent matrix multiplications can be partitioned into smaller matrix multiplications, each of which is localized with respect to which tensor elements are required.Type: GrantFiled: July 20, 2017Date of Patent: September 11, 2018Assignee: NovuMind LimitedInventors: Chien-Ping Lu, Yu-Shuen Tang
-
Patent number: 9786098Abstract: A rendering method executed by a graphics processing unit includes: loading a vertex shading command from a first command queue to a shader module; executing the vertex shading command for computing the varying of the vertices to perform a vertex shading operation by taking the vertices as first input data; storing first tessellation stage commands into a second command queue; loading the first tessellation stage commands to the shader module; and executing the first tessellation commands for computing first tessellation stage outputs to perform a first tessellation stage of the one or more tessellation stages by taking the varying of the vertices as second input data. The vertex shading command is stored into the first command queue by a first processing unit. The varying of the vertices and the first tessellation stage outputs are stored in a cache of the graphics processing unit.Type: GrantFiled: July 6, 2015Date of Patent: October 10, 2017Assignee: MEDIATEK INC.Inventors: Pei-Kuei Tsung, Shou-Jen Lai, Yan-Hong Lu, Sung-Fang Tsai, Chien-Ping Lu
-
Patent number: 9703605Abstract: A heterogeneous computing system described herein has an energy-efficient architecture that exploits producer-consumer locality, task parallelism and data parallelism. The heterogeneous computing system includes a task frontend that dispatches tasks and updated tasks from queues for execution based on properties associated with the queues, and execution units that include a first subset acting as producers to execute the tasks and generate the updated tasks, and a second subset acting as consumers to execute the updated tasks. The execution units includes one or more control processors to perform control operations, vector processors to perform vector operations, and accelerators to perform multimedia signal processing operations. The heterogeneous computing system also includes a memory backend containing the queues to store the tasks and the updated tasks for execution by the execution units.Type: GrantFiled: September 4, 2015Date of Patent: July 11, 2017Assignee: MediaTek, Inc.Inventors: Chien-Ping Lu, Hsilin Huang
-
Patent number: 9659407Abstract: A graphics processing unit (GPU) is provided to preemptively flush one or more bins. The GPU generates bin data of a display area according to an association of primitive data with the bins that correspond to the display area. Upon detecting an adaptive condition, a signal is generated to indicate that one or more bins of a first frame are to be flushed in a first order before the first frame is fully binned. The signal interrupts bin flush of a second frame in a second order in order to flush the one or more bins of the first frame in the first order. After the one or more bins of the first frame are flushed, the bin flush of the second frame is resumed in the second order.Type: GrantFiled: January 26, 2015Date of Patent: May 23, 2017Assignee: MediaTek Singapore, Pte. Lte.Inventors: Chien-Ping Lu, Qun-Feng Liao, Hsilin Huang, Xiayang Zhao
-
Publication number: 20170068571Abstract: A heterogeneous computing system described herein has an energy-efficient architecture that exploits producer-consumer locality, task parallelism and data parallelism. The heterogeneous computing system includes a task frontend that dispatches tasks and updated tasks from queues for execution based on properties associated with the queues, and execution units that include a first subset acting as producers to execute the tasks and generate the updated tasks, and a second subset acting as consumers to execute the updated tasks. The execution units includes one or more control processors to perform control operations, vector processors to perform vector operations, and accelerators to perform multimedia signal processing operations. The heterogeneous computing system also includes a memory backend containing the queues to store the tasks and the updated tasks for execution by the execution units.Type: ApplicationFiled: September 4, 2015Publication date: March 9, 2017Inventors: Chien-Ping LU, Hsilin HUANG
-
Publication number: 20170011550Abstract: A rendering method executed by a graphics processing unit includes: loading a vertex shading command from a first command queue to a shader module; executing the vertex shading command for computing the varying of the vertices to perform a vertex shading operation by taking the vertices as first input data; storing first tessellation stage commands into a second command queue; loading the first tessellation stage commands to the shader module; and executing the first tessellation commands for computing first tessellation stage outputs to perform a first tessellation stage of the one or more tessellation stages by taking the varying of the vertices as second input data. The vertex shading command is stored into the first command queue by a first processing unit. The varying of the vertices and the first tessellation stage outputs are stored in a cache of the graphics processing unit.Type: ApplicationFiled: July 6, 2015Publication date: January 12, 2017Inventors: Pei-Kuei TSUNG, Shou-Jen LAI, Yan-Hong LU, Sung-Fang TSAI, Chien-Ping LU
-
Publication number: 20160217550Abstract: A graphics processing unit (GPU) is provided to preemptively flush one or more bins. The GPU generates bin data of a display area according to an association of primitive data with the bins that correspond to the display area. Upon detecting an adaptive condition, a signal is generated to indicate that one or more bins of a first frame are to be flushed in a first order before the first frame is fully binned. The signal interrupts bin flush of a second frame in a second order in order to flush the one or more bins of the first frame in the first order. After the one or more bins of the first frame are flushed, the bin flush of the second frame is resumed in the second order.Type: ApplicationFiled: January 26, 2015Publication date: July 28, 2016Inventors: Chien-Ping LU, Qun-Feng LIAO, Hsilin HUANG, Xiayang ZHAO
-
Publication number: 20160210231Abstract: A processing unit includes one or more first cores. The one or more first cores and one or more second cores are part of a heterogeneous computing system and share a system memory. Each first core includes a 1st L1 cache that supports snooping by the second cores, and a 2nd L1 cache that does not support snooping. The 1st L1 cache is coupled to and receives cache access requests from an instruction-based computing module of the first core, and the 2nd L1 cache is coupled to and receives cache access requests from a fixed-function pipeline module of the first core. The processing unit also includes a L2 cache that supports snooping. The L2 cache receives cache access requests from the 1st L1 cache and the 2nd L1 cache.Type: ApplicationFiled: January 21, 2015Publication date: July 21, 2016Inventors: Hsilin HUANG, Chien-Ping LU
-
Patent number: 9041374Abstract: A power converting circuit includes an upper gate switch, a transistor, a current source circuit, a comparator circuit, a delay circuit, and a pulse width modulation signal generating circuit. The transistor and the current source circuit provide a reference signal. The comparator circuit generates a comparing signal according to the reference signal and an output signal provided by the upper gate switch. The delay circuit generates a delay signal according to the comparing signal and a clock signal. The pulse width modulation signal generating circuit generates a control signal for the upper gate switch according to the delay signal and the clock signal for configuring the conduction status of the upper gate switch. The power converting circuit adjusts the conduction time of the upper gate switch according to the reference signal and the output signal.Type: GrantFiled: March 12, 2014Date of Patent: May 26, 2015Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Hung-Yu Cheng, Chung-Lung Pai, Tzu Huan Chiu, Chien-Ping Lu
-
Patent number: 8917062Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.Type: GrantFiled: August 29, 2012Date of Patent: December 23, 2014Assignee: Richtek Technology CorporationInventors: Chien-Ping Lu, Nien-Hui Kung, Li-Wei Lee, Chia-Hsiang Lin, Chen-Hsiang Hsiao, Ko-Ching Su
-
Publication number: 20140266133Abstract: A power converting circuit includes an upper gate switch, a transistor, a current source circuit, a comparator circuit, a delay circuit, and a pulse width modulation signal generating circuit. The transistor and the current source circuit provide a reference signal. The comparator circuit generates a comparing signal according to the reference signal and an output signal provided by the upper gate switch. The delay circuit generates a delay signal according to the comparing signal and a clock signal. The pulse width modulation signal generating circuit generates a control signal for the upper gate switch according to the delay signal and the clock signal for configuring the conduction status of the upper gate switch. The power converting circuit adjusts the conduction time of the upper gate switch according to the reference signal and the output signal.Type: ApplicationFiled: March 12, 2014Publication date: September 18, 2014Applicant: Richtek Technology CorporationInventors: Hung-Yu CHENG, Chung-Lung PAI, Tzu Huan CHIU, Chien-Ping LU
-
Publication number: 20140062435Abstract: The present invention discloses a charge control circuit for supplying power from an external power source to a first common node and charging a second common node from the first common node. A regulator circuit is coupled between the external power source and the first common node, and a transistor is coupled between the first common node and the second common node. The present invention detects an operation parameter of the transistor and controls an internal voltage source to generate a non-predetermined voltage difference accordingly. When the sum of the voltage at the second common node and the non-predetermined voltage is equal to or higher than the reference voltage, the voltage at the first common node is regulated to a level higher than the voltage at the second common node, and the transistor is in an optimum conductive state.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Inventors: Chien-Ping Lu, Nien-Hui Kung, Li-Wei Lee, Chia-Hsiang Lin, Chen-Hsiang Hsiao, Ko-Ching Su
-
Patent number: 8638126Abstract: The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.Type: GrantFiled: January 18, 2012Date of Patent: January 28, 2014Assignee: Richtek Technology Corporation, R.O.C.Inventors: Chieh-Min Lo, Tzu-Huan Chiu, Chien-Sheng Chen, Chien-Ping Lu
-
Publication number: 20130293204Abstract: The switching regulator of a buck-boost converter includes a first, a second, a third, and a fourth switches. A control circuit for controlling the switching regulator includes an error detector, a ramp signal generator, a comparator, an oscillator, and a control signal generator. The error detector generates an error signal corresponding to an output voltage of the switching regulator. The ramp signal generator generates a ramp signal. The comparator compares the error signal and the ramp signal to generate a comparison signal. The oscillator generates an oscillating signal. The control signal generator controls the first, the second, the third, and the fourth switches according to the comparison signal, the oscillating signal, and a clock signal, so that the switching regulator is configured to switch only between a boost mode and a buck mode, and not to operate at a buck-boost mode.Type: ApplicationFiled: April 16, 2013Publication date: November 7, 2013Applicant: Richtek Technology CorporationInventor: Chien-Ping LU
-
Patent number: 8547078Abstract: Methods are proposed for a buck boost voltage regulator to monitor the output voltage or both the inductor current and the output voltage of the buck boost voltage regulator to control the buck boost voltage regulator to reduce the switching times of the power switches of the buck boost voltage regulator to improve the light load efficiency of the buck boost voltage regulator.Type: GrantFiled: August 24, 2010Date of Patent: October 1, 2013Assignee: Richtek Technology Corp.Inventors: Tzu-Huan Chiu, Kwan-Jen Chu, Chien-Ping Lu, Wei-Hsin Wei