Patents by Inventor Chien-Shao Tang
Chien-Shao Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10985157Abstract: An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.Type: GrantFiled: September 19, 2019Date of Patent: April 20, 2021Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventors: Chien-Shao Tang, Ting-Jui Lin, Hsiang-Ming Chou, Fang-Yu Chang
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Publication number: 20210091070Abstract: An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.Type: ApplicationFiled: September 19, 2019Publication date: March 25, 2021Inventors: CHIEN-SHAO TANG, TING-JUI LIN, HSIANG-MING CHOU, FANG-YU CHANG
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Patent number: 8995100Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.Type: GrantFiled: March 26, 2012Date of Patent: March 31, 2015Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen
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Publication number: 20130249046Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.Type: ApplicationFiled: March 26, 2012Publication date: September 26, 2013Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen
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Patent number: 8324705Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.Type: GrantFiled: May 27, 2008Date of Patent: December 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Shao Tang, Dah-Chuen Ho, Yu-Chang Jong, Zhe-Yi Wang, Yuh-Hwa Chang, Yogendra Yadav
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Patent number: 8114745Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: GrantFiled: April 14, 2010Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Patent number: 7808069Abstract: A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.Type: GrantFiled: December 31, 2008Date of Patent: October 5, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dah-Chuen Ho, Chien-Shao Tang, Yu-Chang Jong, Zhe-Yi Wang
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Publication number: 20100203691Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: ApplicationFiled: April 14, 2010Publication date: August 12, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Publication number: 20100164050Abstract: A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dah-Chuen HO, Chien-Shao TANG, Yu-Chang JONG, Zhe-Yi WANG
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Patent number: 7719064Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: GrantFiled: April 10, 2008Date of Patent: May 18, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Publication number: 20090294865Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.Type: ApplicationFiled: May 27, 2008Publication date: December 3, 2009Inventors: Chien-Shao Tang, Dah-Chuen Ho, Yu-Chang Jong, Zhe-Yi Wang, Yuh-Hwa Chang, Yogendra Yadav
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Patent number: 7608889Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.Type: GrantFiled: September 28, 2007Date of Patent: October 27, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dah-Chuen Ho, Chien-Shao Tang, Zhe-Yi Wang, Yu-Chang Jong
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Publication number: 20090085112Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dah-Chuen Ho, Chien-Shao Tang, Zhe-Yi Wang, Yu-Chang Jong
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Publication number: 20080191291Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: ApplicationFiled: April 10, 2008Publication date: August 14, 2008Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Patent number: 7372104Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: GrantFiled: December 12, 2005Date of Patent: May 13, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Publication number: 20080073745Abstract: A high-voltage semiconductor structure includes a high-voltage well region overlying a substrate, an isolation region extending from a top surface of the high-voltage well region into the high-voltage well region, a low-voltage well region having at least a portion underlying and adjoining the isolation region wherein the low-voltage well region is inside of and of a same conductivity type as the high-voltage well region, a gate dielectric on the high-voltage well region, a gate electrode on the gate dielectric, and a source/drain region of the same conductivity type as the high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.Type: ApplicationFiled: September 25, 2006Publication date: March 27, 2008Inventors: Chien-Shao Tang, Tsung-Yi Huang, David Ho, Zhe-Yi Wang, Yu-Chang Jong
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Publication number: 20070221999Abstract: A semiconductor device includes a gate electrode, and a source region and a drain region proximate the gate electrode. A silicide region is disposed over a top surface of the gate electrode, the source region, or the drain region. A non-silicide region is disposed proximate the silicide region over an edge region of the top surface of the gate electrode, the source region, or the drain region.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Inventors: Chen-Bau Wu, Jiann-Tyng Tzeng, Chien-Shao Tang
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Publication number: 20070132033Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: ApplicationFiled: December 12, 2005Publication date: June 14, 2007Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu