Abstract: An imaging lens includes a first lens, a second lens, a third lens, a fourth lens and a fifth lens with refractive powers arranged in order from an object side to an image side of the imaging lens. The first lens is closest to the object side as compared with any other lens with a refractive power in the imaging lens, and the fifth lens is closest to the image side as compared with any other lens with a refractive power in the imaging lens. The imaging lens satisfies the conditions of 0.5<D1/LT<0.8 and 0.5<DL/LT<0.8, where D1 is a lens diameter of the first lens, DL is a lens diameter of the fifth lens, and LT is a distance measured along an optical axis between an object-side surface of the first lens and an image-side surface of the fifth lens.

Abstract: A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N− contact areas. An N+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N+ and P+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N− contacts, while forming metal landing plugs to the N+ and P+ contacts.

Abstract: A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer.

Abstract: A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N.sup.- contact areas. An N.sup.+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N.sup.+ and P.sup.+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N.sup.- contacts, while forming metal landing plugs to the N.sup.+ and P.sup.+ contacts.