Patents by Inventor Chien-Sheng Lin
Chien-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240407079Abstract: A carrier structure is provided, in which a ground layer is formed on a dielectric body, a circuit layer is formed in the dielectric body, and a conductive via is formed in the dielectric body and electrically connected to the circuit layer and the ground layer, where the ground layer has at least one first groove that exposes a surface of the dielectric body, so that the noise of the circuit layer is easy to spread out of the dielectric body, so as to prevent the problem of crosstalk from occurring in the circuit layer.Type: ApplicationFiled: August 30, 2023Publication date: December 5, 2024Inventors: Chien-Sheng CHEN, Chia-Chu LAI, Ho-Chuan LIN
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Patent number: 12149198Abstract: A method of adaptively controlling a brushless DC motor includes steps of: controlling the brushless DC motor rotating at a first speed according to an operation curve, accumulating a running time of the brushless DC motor, estimating a remaining used time of a bearing of the brushless DC motor according to the accumulated running time, executing an alarm operation when the remaining used time is less than a predetermined time, and decreasing the speed of the brushless DC motor to run at a second speed to prolong the used time of the bearing.Type: GrantFiled: August 23, 2022Date of Patent: November 19, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chia-Feng Wu, Chien-Sheng Lin, Jou-Sheng Wang
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Patent number: 12148723Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.Type: GrantFiled: December 7, 2022Date of Patent: November 19, 2024Assignee: United Microelectronics Corp.Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
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Publication number: 20240371743Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.Type: ApplicationFiled: July 18, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hung Chen, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
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Publication number: 20240371792Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a warpage-control element laterally surrounding the chip-containing structure. The warpage-control element has a protruding portions extending into the substrate.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng LIN, Chien-Hung CHEN, Po-Chen LAI, Po-Yao LIN, Shin-Puu JENG
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Patent number: 12136952Abstract: Disclosed are a co-packaged integrated optoelectronic module and a co-packaged optoelectronic switch chip. The co-packaged integrated optoelectronic module includes a carrier board, and an optoelectronic submodule, a slave microprocessor and a master microprocessor disposed on and electrically connected to the carrier board. In the optoelectronic submodule, a digital signal processing chip converts an electrical analog signal into an electrical digital signal, an optoelectronic signal analog conversion chip converts an optical analog signal into the electrical analog signal to the digital signal processing chip, and an optical transceiver chip receives and transmits the optical analog signal to the optoelectronic signal analog conversion chip. The slave microprocessor monitors operation of the optoelectronic submodule.Type: GrantFiled: August 10, 2022Date of Patent: November 5, 2024Assignee: DONGGUAN LUXSHARE TECHNOLOGIES CO., LTDInventors: Min-Sheng Kao, ChunFu Wu, Chung-Hsin Fu, QianBing Yan, LinChun Li, Chih-Wei Yu, Chien-Tzu Wu, Yi-Tseng Lin
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Publication number: 20240363517Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Han-Hsiang Huang, Chien-Sheng Chen, Shu-Shen Yeh, Shin-Puu Jeng
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Patent number: 12120843Abstract: A fan management system includes a fan and a server. The fan includes a driving circuit, and the driving circuit is configured for driving the fan. The fan operates in an operation mode. The server is connected to the fan and is configured for controlling the operation of the fan. The driving circuit outputs a digital label signal when the fan operates abnormally, and the server obtains a production history, an operation information and a warning message of the fan through the digital label signal. The server adjusts the operation mode of the fan according to the warning message simultaneously.Type: GrantFiled: September 14, 2021Date of Patent: October 15, 2024Assignee: Delta Electronics, Inc.Inventors: Chia-Feng Wu, Chien-Sheng Lin, Ming-Lung Liu, Hsin-Ming Hsu, Yun-Hua Chao, Po-Tsun Chen, Yueh-Lung Huang, Jung-Yuan Chen, Yu-Cheng Lin
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Patent number: 12119296Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.Type: GrantFiled: August 2, 2023Date of Patent: October 15, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hung Chen, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 12092882Abstract: An optical electrical connector includes a casing, a printed circuit board, an electronic chip, a photoelectric conversion component, and a heat sink device. The casing includes an electrical port and an optical port. A receiving space is defined between the electrical port and the optical port. The printed circuit board extends longitudinally along a first direction. The printed circuit board includes a main body portion located in the receiving space and a front end portion exposed in the electrical port. The electronic chip, the photoelectric conversion component and the heat sink device are all accommodated in the receiving space. The electronic chip and the photoelectric conversion component are not only disposed on the printed circuit board, but also electrically connected to the printed circuit board. The heat sink device is disposed on the casing and faces the electronic chip for conducting the heat accumulated on the electronic chip.Type: GrantFiled: July 6, 2022Date of Patent: September 17, 2024Assignee: DONGGUAN LUXSHARE TECHNOLOGIES CO., LTDInventors: Yi-Tseng Lin, Chih-Wei Yu, Chien-Tzu Wu, Kuen-Da Jeng, Min-Sheng Kao
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Patent number: 12087705Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure bonded to the substrate. The package structure also includes a warpage-control element attached to the substrate. The warpage-control element has a protruding portion extending into the substrate.Type: GrantFiled: April 21, 2023Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Lin, Chien-Hung Chen, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 12074101Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.Type: GrantFiled: September 22, 2023Date of Patent: August 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Han-Hsiang Huang, Chien-Sheng Chen, Shu-Shen Yeh, Shin-Puu Jeng
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Publication number: 20240266190Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.Type: ApplicationFiled: April 22, 2024Publication date: August 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsiung LU, Ming-Da CHENG, Su-Fei LIN, Hsu-Lun LIU, Chien-Pin CHAN, Yung-Sheng LIN
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Publication number: 20220416695Abstract: A method of adaptively controlling a brushless DC motor includes steps of: controlling the brushless DC motor rotating at a first speed according to an operation curve, accumulating a running time of the brushless DC motor, estimating a remaining used time of a bearing of the brushless DC motor according to the accumulated running time, executing an alarm operation when the remaining used time is less than a predetermined time, and decreasing the speed of the brushless DC motor to run at a second speed to prolong the used time of the bearing.Type: ApplicationFiled: August 23, 2022Publication date: December 29, 2022Inventors: Chia-Feng WU, Chien-Sheng LIN, Jou-Sheng WANG
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Patent number: 11340691Abstract: A heat dissipation apparatus with energy-saving effect is coupled to an operation unit, and the heat dissipation apparatus includes a control unit and a drive circuit. The control unit determines whether the operation unit enters an energy-saving mode according to a first signal provided by the operation unit. The control unit shields a plurality of second signals provided to the drive circuit according to the energy-saving mode. The drive circuit does not drive the heat dissipation unit and the heat dissipation unit enters an inertia deceleration.Type: GrantFiled: April 18, 2020Date of Patent: May 24, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Chia-Feng Wu, Po-Hui Shen, Chien-Sheng Lin, Chun-Chieh Tsai, Chia-Wei Hsu, Rou-Sheng Wang
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Publication number: 20220087060Abstract: A fan management system includes a fan and a server. The fan includes a driving circuit, and the driving circuit is configured for driving the fan. The fan operates in an operation mode. The server is connected to the fan and is configured for controlling the operation of the fan. The driving circuit outputs a digital label signal when the fan operates abnormally, and the server obtains a production history, an operation information and a warning message of the fan through the digital label signal. The server adjusts the operation mode of the fan according to the warning message simultaneously.Type: ApplicationFiled: September 14, 2021Publication date: March 17, 2022Inventors: Chia-Feng Wu, Chien-Sheng Lin, Ming-Lung Liu, Hsin-Ming Hsu, Yun-Hua Chao, Po-Tsun Chen, Yueh-Lung Huang, Jung-Yuan Chen, Yu-Cheng Lin
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Publication number: 20210148788Abstract: A method of estimating used time of a brushless DC motor is provided. The method includes steps of: calculating a running time of the brushless DC motor when the brushless DC motor is in a normal operation state, recording the running time when the brushless DC motor is in an abnormal operation state, updating an accumulated running time, estimating a used time of a bearing of the brushless DC motor according to the accumulated running time, and determining a life span of the bearing according to the used time of the bearing.Type: ApplicationFiled: January 26, 2021Publication date: May 20, 2021Inventors: Chia-Feng WU, Chien-Sheng LIN, Jou-Sheng WANG
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Publication number: 20210089111Abstract: A heat dissipation apparatus with energy-saving effect is coupled to an operation unit, and the heat dissipation apparatus includes a control unit and a drive circuit. The control unit determines whether the operation unit enters an energy-saving mode according to a first signal provided by the operation unit. The control unit shields a plurality of second signals provided to the drive circuit according to the energy-saving mode. The drive circuit does not drive the heat dissipation unit and the heat dissipation unit enters an inertia deceleration.Type: ApplicationFiled: April 18, 2020Publication date: March 25, 2021Inventors: Chia-Feng WU, Po-Hui SHEN, Chien-Sheng LIN, Chun-Chieh TSAI, Chia-Wei HSU, Rou-Sheng WANG
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Publication number: 20200144953Abstract: A brushless DC motor with automatic record of abnormal operation includes an integrated circuit chip electrically connected to a drive circuit of the brushless DC motor. The integrated circuit chip includes a central processing unit, and a flash memory and a detection unit connected to the central processing unit. When the detection unit receives a detection signal from the drive circuit and the central processing unit determines that the brushless DC motor is in an abnormal operation state, the central processing unit generates an abnormal operation data including an error code so that the flash memory automatically stores the abnormal operation data. The present disclosure further includes a method of automatically recording abnormality for the brushless DC motor.Type: ApplicationFiled: May 29, 2019Publication date: May 7, 2020Inventors: Chia-Feng WU, Chien-Sheng LIN, Jou-Sheng WANG
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Patent number: 9973118Abstract: A motor drive circuit including a back electromotive force detecting module and a processing module is disclosed herein. The back electromotive force detecting module is electrically connected to a single phase DC motor and is configured to detect a back electromotive force of the single phase DC motor and to output a detecting signal correspondingly. The processing module is electrically connected to the back electromotive force detecting module and the single phase DC motor. The processing module is configured to determine the rotation direction of the single phase DC motor according to the detecting signal and a hall signal outputted by a hall element located in the single phase DC motor, and is configured to control the single phase DC motor.Type: GrantFiled: August 20, 2015Date of Patent: May 15, 2018Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Liang Lin, Chung-Hung Tang, Cheng-Chieh Liu, Chien-Sheng Lin, Chun-Lung Chiu