Patents by Inventor Chien-Shian Peng

Chien-Shian Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patterned conductor layer pasivation method with dimensionally stabilized planarization
    Patent number: 6534396
    Abstract: Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: March 18, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Jier Fahn, Kuo-Wei Lin, James Chen, Eugene Cheu, Chien-Shian Peng, Gilbert Fan, Kenneth Lin