Abstract: The present invention provides an apparatus. The apparatus, in one embodiment, includes an actuator located over a substrate, a movable feature located over and coupled to the actuator, and a layer of material located above the actuator and movable feature and not constituting part of a beam/spring associated with the movable feature, the layer of material configured as a reservoir having an interior capable of holding a liquid, the movable feature being exposed to the interior.

Abstract: The present invention provides an apparatus. The apparatus, may include an actuator located over a substrate, a movable feature located over and coupled to the actuator, and a layer of material located above the actuator and movable feature and not constituting part of a beam/spring associated with the movable feature, the layer of material configured as a reservoir having an interior capable of holding a liquid, the movable feature being exposed to the interior.

Abstract: The present invention provides a process for manufacturing an apparatus. The process, in one embodiment, includes providing a micro-electro-mechanical system (MEMS) device, the micro-electro-mechanical system (MEMS) device including an actuator coupled to a movable feature, sacrificial material fixing the actuator and movable feature with respect to one another, and a layer of material located over the actuator, movable feature and sacrificial material. The process may further include removing only a portion of the layer of material to expose the sacrificial material, and subjecting the exposed sacrificial material to an etchant to release the movable feature.

Abstract: A chemical reactor includes two substrates that are joined along a surface and a chemical reaction chamber formed between the substrates. The chemical reaction chamber has a hollow interior and one or more light reflectors located along walls of the hollow interior. The chemical reaction chamber has one or more inputs to transport fluid into the hollow interior and an output to transport fluid out of the hollow interior. The one or more light reflectors cause light rays to make multiple crossings of the hollow interior as a result of reflections off the one or more reflectors.

Abstract: The present invention provides a process and an apparatus. The process, in one embodiment, includes providing a micro-electro-mechanical system (MEMS) device, the micro-electro-mechanical system (MEMS) device including an actuator coupled to a movable feature, sacrificial material fixing the actuator and movable feature with respect to one another, and a layer of material located over the actuator, movable feature and sacrificial material. The process may further include removing only a portion of the layer of material to expose the sacrificial material, and subjecting the exposed sacrificial material to an etchant to release the movable feature.

Abstract: An apparatus for an ion trap includes a semiconductor or dielectric wafer with front and back surfaces, a sequence of alternating conductive and dielectric layers formed over said front surface, and a bottom conductive layer. The sequence includes top and middle conductive layers, wherein the middle conductive layer is closer to the wafer than the top conductive layer. The middle conductive layer includes a substantially right cylindrical cavity that crosses a width of the middle conductive layer. The top and bottom conductive layers cap respective first and second ends of the cavity. The top conductive layer includes a hole that forms a first access port to the cavity. The wafer includes via through the width of the wafer. The via provides another access to the cavity via the back surface of the wafer. The wafer is substantially thicker than the sequence of layers.

Abstract: An apparatus includes a semiconductor or dielectric wafer-substrate and first and second multi-layer structures located over the wafer-substrate. The first multi-layer structure includes an ionizer or an electronic ion detector. The second multi-layer structure includes an ion trap having entrance and exit ports. The ionizer or electronic ion detector has a port coupled to one of the ports of the ion trap.

Abstract: An apparatus includes a semiconductor or dielectric wafer-substrate and first and second multi-layer structures located over the wafer-substrate. The first multi-layer structure includes an ionizer or an electronic ion detector. The second multi-layer structure includes an ion trap having entrance and exit ports. The ionizer or electronic ion detector has a port coupled to one of the ports of the ion trap.

Abstract: An apparatus for an ion trap includes a semiconductor or dielectric wafer with front and back surfaces, a sequence of alternating conductive and dielectric layers formed over said front surface, and a bottom conductive layer. The sequence includes top and middle conductive layers, wherein the middle conductive layer is closer to the wafer than the top conductive layer. The middle conductive layer includes a substantially right cylindrical cavity that crosses a width of the middle conductive layer. The top and bottom conductive layers cap respective first and second ends of the cavity. The top conductive layer includes a hole that forms a first access port to the cavity. The wafer includes via through the width of the wafer. The via provides another access to the cavity via the back surface of the wafer. The wafer is substantially thicker than the sequence of layers.

Abstract: A process for fabricating an integrated semiconductor device with a low dielectric constant material and an integrated semiconductor device with the low dielectric constant material interposed between two conductors is disclosed. The low dielectric constant material has a dielectric constant of less than about 2.8. The low dielectric constant material is a porous glass material with an average pore size of less than about 10 nm. The low dielectric constant material is formed on a semiconductor substrate with circuit lines thereover by combining an uncured and unmodified glass resin with an amphiphilic block copolymer. The amphiphilic block copolymer is miscible in the uncured glass resin. The mixture is applied onto the semiconductor substrate and the glass resin is cured. The glass resin is further processed to decompose or otherwise remove residual block copolymer from the cured glass resin.

Abstract: In fabricating an apparatus such as a silicon device or an optical device initially a wafer having a plurality of dies is formed. These dies are then separated into individual dies and the individual dies are formed into encapsulated devices having input and/or output leads. The dies are separated by a means that is not based on crystallographic plane cleavage. Additionally the boundary along which the separation is performed is not a linear path. By employing non-linear paths that are not constrained by crystallographic planes, device yield per wafer is substantially improved particularly for dies having non-linear boundaries. In one embodiment the dies are separated using an alternating dry etching and polymer deposition technique.

Abstract: A chemical reactor includes two substrates that are joined along a surface and a chemical reaction chamber formed between the substrates. The chemical reaction chamber has a hollow interior and one or more light reflectors located along walls of the hollow interior. The chemical reaction chamber has one or more inputs to transport fluid into the hollow interior and an output to transport fluid out of the hollow interior. The one or more light reflectors cause light rays to make multiple crossings of the hollow interior as a result of reflections off the one or more reflectors.

Abstract: A semiconductor device, and a process for fabricating the device, is disclosed. The semiconductor device is an MOS device in which the gate is bounded by spacers, which are in turn bounded by a trench in a trench dielectric layer formed on a semiconductor substrate. The device is formed by lithographically defining a sacrificial gate on the surface of the semiconductor substrate. The trench dielectric layer is then formed on the semiconductor substrate and adjacent to the sacrificial gate. The trench dielectric layer is planarized and, subsequent to planarization, the sacrificial gate is no longer covered by the trench dielectric layer. The sacrificial gate is then removed, which leaves a trench in the trench dielectric layer. Dielectric spacers are then formed in the trench. The distance between the spacers defines the gate length of the semiconductor device. After the spacers are formed, the device gate is formed. At least a portion of the gate is formed in the trench.

Abstract: A process for fabricating an integrated semiconductor device with a low dielectric constant material and an integrated semiconductor device with the low dielectric constant material interposed between two conductors is disclosed. The low dielectric constant material has a dielectric constant of less than about 2.8. The low dielectric constant material is a porous glass material with an average pore size of less than about 10 nm. The low dielectric constant material is formed on a semiconductor substrate with circuit lines thereover by combining an uncured and unmodified glass resin with an amphiphilic block copolymer. The amphiphilic block copolymer is miscible in the uncured glass resin. The mixture is applied onto the semiconductor substrate and the glass resin is cured. The glass resin is further processed to decompose or otherwise remove residual block copolymer from the cured glass resin.

Abstract: The invention is a process for device fabrication that utilizes shallow trench isolation. The process involves the steps of forming an oxidation barrier region, e.g., silicon nitride, above a silicon substrate, providing an opening in the oxidation barrier region and in any underlying regions deposited on the silicon, providing a trench in the silicon substrate at the opening, depositing a dielectric material such as silicon dioxide in the trench, typically planarizing the trench silicon dioxide, and subsequently performing an oxidation step. The oxidation step rounds the otherwise sharp corners of the silicon at the area where the trench silicon dioxide meets the pad oxide. The invention thereby reduces or eliminates sharp corners that contribute to leakage current.

Abstract: It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

Abstract: A process for fabricating a silicon-on-insulator integrated circuit in conjunction with a process for shallow trench isolation is disclosed. The shallow trench isolation is performed to define active regions in the silicon substrate. The active regions are electrically isolated from each other by regions of silicon dioxide formed in the substrate by the shallow trench isolation process. The height of the silicon dioxide regions above the substrate surface defines the combined thickness of the islands of silicon dioxide and the silicon formed over the islands of silicon dioxide. A mask is then formed on the silicon substrate with the regions of silicon dioxide formed therein. The mask defines the regions on the silicon substrate surface on which the islands of silicon dioxide are to be formed. The silicon dioxide islands are formed with the mask in place, and the mask is subsequently removed. Single crystal silicon is formed epitaxially on the structure.

Abstract: It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

Abstract: Ion beam deposition, using a carbon- and fluorine-containing source or sources, is used to form a fluorinated diamond-like carbon layer in a device, the FDLC layer exhibiting a dielectric constant of 3.0 or less along with a thermal stability of at least 400° C. During the ion beam deposition, due to the unique nature of carbon chemistry, the carbon atoms combine at the substrate surface to form all possible combinations of sp1, sp2 and sp3 bonds. However, ion beam etching occurs along with deposition, such that atoms of the weaker carbon structures—carbyne and graphite—are removed preferentially. This leads to a buildup of a diamond-like, sp3-bonded structure with fluorine atoms, it is believed, substituted for some carbon atoms within the structure, this structure providing the desirable properties of the layer.

Abstract: The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.