Patents by Inventor Chien-Te Chen
Chien-Te Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12193166Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.Type: GrantFiled: April 13, 2022Date of Patent: January 7, 2025Assignee: Sandisk Technologies, Inc.Inventors: Songtao Lu, Hsiang Ju Huang, Binbin Zheng, Cheng-Hsiung Yang, Chien-Te Chen
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Patent number: 12022618Abstract: A substrate of an electronic device includes a first set of contact pads and a first set of contact pillars having a height greater than the first set of contact pads. Components are coupled to the first set of contact pads and the first set of contact pillars in traversing directions. The components coupled to the contact pillars are positioned above the components coupled to the first set of contact pads such that at least a first portion of a first side of the component coupled to the contact traces faces a first side of the components coupled to the contact pillars. Stacking passive components in this manner can allow for increased component density without increasing package size.Type: GrantFiled: April 22, 2021Date of Patent: June 25, 2024Assignee: Western Digital Technologies, Inc.Inventors: Chien Te Chen, Cong Zhang, Yu Ying Tan, Hsiao Jung Lin, Chieh Kai Yang
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Publication number: 20240120317Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.Type: ApplicationFiled: July 13, 2023Publication date: April 11, 2024Applicant: Western Digital Technologies, Inc.Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
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Patent number: 11924964Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.Type: GrantFiled: April 7, 2022Date of Patent: March 5, 2024Assignee: Western Digital Technologies, Inc.Inventors: Lin Hui Chen, Songtao Lu, Chien Te Chen, Yu Ying Tan, Huang Pao Yi, Ching Chuan Hsieh, T. Sharanya Kaminda, Chia-Hsuan Huang
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Publication number: 20230337372Abstract: In one example, the present application describes a Printed Circuit Board (PCB) that mitigates galvanic corrosion during an Organic Solderability Preservative (OSP) process used during fabrication of the PCB. The PCB includes a first metal pattern and a second metal pattern electrically coupled to each other, where the first and second metal patterns are different metals. The first metal pattern has a first area that is exposed by a solder mask layer, and the second metal pattern has a second area that is exposed by the solder mask area. A ratio of the first area to the second area is less than a threshold ratio to mitigate the galvanic corrosion of the second metal pattern exposed on the PCB during the OSP process.Type: ApplicationFiled: April 13, 2022Publication date: October 19, 2023Inventors: Songtao Lu, Hsiang Ju Huang, Binbin Zheng, Cheng-Hsiung Yang, Chien-Te Chen
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Publication number: 20230328873Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Inventors: Lin Hui Chen, Songtao Lu, Chien Te Chen, Yu Ying Tan, Huang Pao Yi, Ching Chuan Hsieh, T. Sharanya Kaminda, Chia-Hsuan Huang
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Patent number: 11557555Abstract: A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.Type: GrantFiled: June 10, 2020Date of Patent: January 17, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Hsiao Jung Lin, Ai Wen Wang, Chien Te Chen, Chieh kai Yang
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Publication number: 20220346234Abstract: A substrate of an electronic device includes a first set of contact pads and a first set of contact pillars having a height greater than the first set of contact pads. Components are coupled to the first set of contact pads and the first set of contact pillars in traversing directions. The components coupled to the contact pillars are positioned above the components coupled to the first set of contact pads such that at least a first portion of a first side of the component coupled to the contact traces faces a first side of the components coupled to the contact pillars. Stacking passive components in this manner can allow for increased component density without increasing package size.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Chien Te Chen, Cong Zhang, Yu Ying Tan, Hsiao Jung Lin, Chieh Kai Yang
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Publication number: 20210391286Abstract: A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.Type: ApplicationFiled: June 10, 2020Publication date: December 16, 2021Applicant: Western Digital Technologies, Inc.Inventors: Hsiao Jung LIN, Ai Wen WANG, Chien Te CHEN, Chieh kai YANG
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Patent number: 11139277Abstract: A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.Type: GrantFiled: March 10, 2020Date of Patent: October 5, 2021Assignee: Western Digital Technologies, Inc.Inventors: Chien Te Chen, Cong Zhang, Hsiang Ju Huang, Xuyi Yang, Yu Ying Tan, Han-Shiao Chen
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Publication number: 20200411478Abstract: A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.Type: ApplicationFiled: March 10, 2020Publication date: December 31, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Chien Te Chen, Cong Zhang, Hsiang Ju Huang, Xuyi Yang, Yu Ying Tan, Han-Shiao Chen
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Patent number: 8772647Abstract: Methods for the formation of single-cap VIPs in a substrate are described herein. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.Type: GrantFiled: April 10, 2012Date of Patent: July 8, 2014Assignee: Marvell International LtdInventor: Chien Te Chen
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Patent number: 8161635Abstract: Novel methods are provided that results in the formation of single-cap VIPs in a substrate are described herein. As a result, fine pitch trace patterns may be formed on the substrate. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.Type: GrantFiled: February 5, 2008Date of Patent: April 24, 2012Assignee: Marvell International Ltd.Inventor: Chien Te Chen
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Publication number: 20090020323Abstract: A circuit board structure and a method for fabricating the same are disclosed, including providing a core board having conductive traces and solder pads respectively formed thereon, wherein width of the solder pads corresponds to that of the conductive traces, and pitch between adjacent solder pads is made wide enough to allow multiple conductive traces to pass through; forming on the core board an insulating layer with openings for exposing the solder pads therefrom; forming on the insulating layer a plurality of extending pads electrically connected to the solder pads respectively, wherein the projection area of the extending pads is larger than that of the corresponding solder pads and covers conductive traces adjacent to the corresponding solder pads. Thus, more conductive traces are allowed to pass between adjacent solder pads and meanwhile, the extending pads provide an effective solder ball wetting area for achieving good solder joints and sufficient height after collapse.Type: ApplicationFiled: July 18, 2008Publication date: January 22, 2009Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Te Chen, Ke-Chuan Yang, Hung-Ming Chang
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Publication number: 20080277144Abstract: A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.Type: ApplicationFiled: July 21, 2008Publication date: November 13, 2008Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chien-Te Chen, Chih-Hao Chang
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Patent number: 7427968Abstract: An antenna device includes an antenna housing having a chamber and a slot formed in one end and formed between two arms and communicating with the chamber, an antenna member having a stud engaged into the slot and rotatably coupled to the antenna housing with a pivot axle and having two or more flat surfaces formed in the stud. A spring-biased follower is slidably received in the antenna housing and includes an actuator for engaging with either of the flat surfaces of the antenna member and for anchoring and retaining the antenna member to the antenna housing at selected angular positions. The antenna device includes a greatly simplified structure with a greatly reduced expense.Type: GrantFiled: June 7, 2006Date of Patent: September 23, 2008Assignee: Joymax Electronics Co., Ltd.Inventors: Yat To Chan, Chien Te Chen
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Patent number: 7402755Abstract: A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.Type: GrantFiled: September 7, 2004Date of Patent: July 22, 2008Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Te Chen, Chih-Hao Chang
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Patent number: 7361846Abstract: A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.Type: GrantFiled: October 26, 2004Date of Patent: April 22, 2008Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Jung Chiang, Chien-Te Chen, Yu-Po Wang
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Publication number: 20070285333Abstract: An antenna device includes an antenna housing having a chamber and a slot formed in one end and formed between two arms and communicating with the chamber, an antenna member having a stud engaged into the slot and rotatably coupled to the antenna housing with a pivot axle and having two or more flat surfaces formed in the stud. A spring-biased follower is slidably received in the antenna housing and includes an actuator for engaging with either of the flat surfaces of the antenna member and for anchoring and retaining the antenna member to the antenna housing at selected angular positions. The antenna device includes a greatly simplified structure with a greatly reduced expense.Type: ApplicationFiled: June 7, 2006Publication date: December 13, 2007Inventors: Yat To Chan, Chien Te Chen
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Patent number: D687692Type: GrantFiled: November 9, 2012Date of Patent: August 13, 2013Inventor: Chien-Te Chen