Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary semiconductor structure includes a substrate, a dielectric layer over the substrate, memory cells disposed in the dielectric layer, and a metal line above the memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. A bottom surface of the metal line has a continuously flat portion that directly interfaces each of the top electrodes of the memory cells.

Abstract: A device comprises a gate structure, n-type source/drain features, p-type source/drain features, an NFET channel, and a PFET channel. The gate structure is over a substrate. The n-type source/drain features are on opposite first and second sides of the gate structure, respectively. The p-type source/drain features are on opposite third and fourth sides of the gate structure, respectively. The NFET channel extends within the gate structure and connects the n-type source/drain features. The PFET channel extends within the gate structure and connects the p-type source/drain features. The NFET channel and the PFET channel are vertically spaced apart by the gate structure.

Abstract: A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.

Abstract: A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

Abstract: A resin composition is provided, which comprises: 75 parts by weight of vinyl group-containing polyphenylene ether resin; 35 parts by weight to 60 parts by weight of an insoluble flame retardant; and 0.4 parts by weight to 5 parts by weight of a compound represented by the following formula (1): wherein R1, R2, R3 and n are defined in the specification. The present invention also provides an article manufactured using the aforesaid resin composition.

Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature, and while the NVM array is heated to the target temperature, programming a subset of the NVM cells to first resistance levels and obtaining a first current distribution, programming the subset of NVM cells to second resistance levels and obtaining a second current distribution, calculating a current threshold level from the first and second current distributions, and for each of the NVM cells, programing the NVM cell to one of the first or second resistance levels, and using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level. A bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the first and second P/F status of each of the NVM cells.

Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconducting material layer, a gate electrode under the semiconducting material layer, a pair of contact terminals over the semiconducting material layer, and a hydrogen-blocking dielectric layer on the semiconducting material layer. The pair of contact terminals penetrates through the hydrogen-blocking dielectric layer to be in contact with the semiconducting material layer at a contact surface, and the contact surface is substantially coplanar with and levelled with an interface between the hydrogen-blocking dielectric layer and the semiconducting material layer.

Abstract: It is checked, using machine learning, whether at least one fail bit in a memory block of a memory is unrepairable, according to a location of the at least one fail bit, and an available repair resource in the memory. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a CSP containing constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to the checking, using the machine learning, indicating that the at least one fail bit is unrepairable, the memory block is marked as unrepairable or the memory is rejected, without making further determinations as to repairability of the memory block.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

Abstract: An optical transceiver includes a housing and an optical transceiving module. The housing includes a main body and a heat conductive component. The heat conductive component is disposed on the main body, and a thermal conductivity of the heat conductive component is larger than a thermal conductivity of the main body. The optical transceiving module is disposed in an accommodation space of the main body of the housing.

Abstract: An optical transceiver includes a housing and an optical transceiving module. The housing includes a main body and a heat conductive component. The heat conductive component is disposed on the main body, and a thermal conductivity of the heat conductive component is larger than a thermal conductivity of the main body. The optical transceiving module is disposed in an accommodation space of the main body of the housing.

Abstract: An optical transceiver includes a photoelectric converter, an interposer and a circuit board. The interposer is disposed on the photoelectric converter. The interposer includes a board member and a flexible electrically conductive member disposed on the board member, and the photoelectric converter is electrically connected to the flexible electrically conductive member. The circuit board is disposed on a side of the interposer. The flexible electrically conductive member is remove-ably pressed against the circuit board so that the flexible conductive member is electrically connected to the circuit board.

Abstract: An optical transceiver includes a photoelectric converter, an interposer and a circuit board. The interposer is disposed on the photoelectric converter. The interposer includes a board member and a flexible electrically conductive member disposed on the board member, and the photoelectric converter is electrically connected to the flexible electrically conductive member. The circuit board is disposed on a side of the interposer. The flexible electrically conductive member is remove-ably pressed against the circuit board so that the flexible conductive member is electrically connected to the circuit board.

Abstract: A pluggable optical transceiver module for being plugged in a housing is provided. The housing has a cover and an elastic piece, and the cover has an accommodating space. One end of the elastic piece is connected to the cover while the other end has a first fastening portion. The first fastening portion is located on one side of the accommodating space. The pluggable optical transceiver module comprises a base and a sliding member. The base comprises a base body and a second fastening portion. The base body has a guide surface, and the second fastening portion is next to the guide surface. The base is for being plugged in the accommodating space, and the second fastening portion is fastened with the first fastening portion. The sliding member comprises a body section and a push section connected to each other. The body section is slidably disposed on the base.

Abstract: A pluggable optical transceiver module for inserted into plugging slot includes main body and sliding component. The main body has opposite two side surfaces and two sliding slots. The two sliding slots are located at the two side surfaces. The sliding component includes linkage arm and two extending arms. The two extending arms are connected to the linkage arm. Each extending arm has a second fastening part. The main body is between the two extending arms. The two extending arms are disposed on the two sliding slots to have fastening position and releasing position. Two first fastening parts are fastened to the two second fastening parts when the two extending arms are located at fastening position. The two second fastening parts press the two first fastening parts, respectively, for the two first fastening parts being farther from each other when the two extending arms are located at releasing position.

Abstract: A pluggable optical transceiver module for being plugged in a housing is provided. The housing has a cover and an elastic piece, and the cover has an accommodating space. One end of the elastic piece is connected to the cover while the other end has a first fastening portion. The first fastening portion is located on one side of the accommodating space. The pluggable optical transceiver module comprises a base and a sliding member. The base comprises a base body and a second fastening portion. The base body has a guide surface, and the second fastening portion is next to the guide surface. The base is for being plugged in the accommodating space, and the second fastening portion is fastened with the first fastening portion. The sliding member comprises a body section and a push section connected to each other. The body section is slidably disposed on the base.

Abstract: A pluggable optical transceiver module for inserted into plugging slot includes main body and sliding component. The main body has opposite two side surfaces and two sliding slots. The two sliding slots are located at the two side surfaces. The sliding component includes linkage arm and two extending arms. The two extending arms are connected to the linkage arm. Each extending arm has a second fastening part. The main body is between the two extending arms. The two extending arms are disposed on the two sliding slots to have fastening position and releasing position. Two first fastening parts are fastened to the two second fastening parts when the two extending arms are located at fastening position. The two second fastening parts press the two first fastening parts, respectively, for the two first fastening parts being farther from each other when the two extending arms are located at releasing position.