Patents by Inventor Chien-Te TU

Chien-Te TU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149172
    Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
  • Patent number: 11233120
    Abstract: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: January 25, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En Tsai, Chia-Che Chung, Chee-Wee Liu, Fang-Liang Lu, Yu-Shiang Huang, Hung-Yu Yeh, Chien-Te Tu, Yi-Chun Liu
  • Publication number: 20210328012
    Abstract: A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU