Abstract: An electronic device and a control method for memory refresh operation thereof are provided. The electronic device includes a memory and a controller. The memory includes a plurality of timers, a plurality of buffers and an interrupt signal generator. Each of the buffers is configured to store at least one word line information, and generate a refresh word line information according to a timing result trigger signal of each corresponding timer. The interrupt signal generator generates an interrupt signal corresponding to an auto refresh operation according to the timing result trigger signal, a non-internal self-refresh mode signal and a non-accessing status. The controller receives the interrupt signal and transmits an auto refresh command to the memory according to the interrupt signal to enable the memory to perform the auto refresh operation.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: A pseudo static memory device includes multiple memories, an arbiter and a controller. The memories respectively generate multiple self-refresh request signals. Each of the self-refresh request signals indicates a time period for performing self-refresh operation of corresponding memory. The arbiter receives the self-refresh request signals and generates a latency synchronize flag during the memories being enabled. The controller decides an accessing latency for accessing the memories during an accessing operation according to the latency synchronize flag.

Abstract: A memory operation method applicable to a memory storage device is provided. The memory operation method including the following steps: receiving, from a memory controller, a first operation command for performing a first memory operation on a memory array of the memory storage device; and in response to the first operation command, transmitting first address information of the memory array corresponding to the first memory operation to the memory controller through a data interface of the memory storage device. In addition, a memory storage device using the memory operation method is also provided.

Abstract: A pseudo static memory device includes multiple memories, an arbiter and a controller. The memories respectively generate multiple self-refresh request signals. Each of the self-refresh request signals indicates a time period for performing self-refresh operation of corresponding memory. The arbiter receives the self-refresh request signals and generates a latency synchronize flag during the memories being enabled. The controller decides an accessing latency for accessing the memories during an accessing operation according to the latency synchronize flag.

Abstract: A memory apparatus and an operation method thereof are provided. The memory apparatus includes a mode configuration register, a system memory array, a pointer and an arithmetic circuit including logic operation units. The mode configuration register stores weight matrix information and a base address. The system memory array stores feature values in a feature map from the base address according to the weight matrix information. The pointer stores the base address and a weight matrix size to provide pointer information. The arithmetic circuit sequentially or parallelly reads the feature values according to the pointer information. The arithmetic circuit parallelly arranges weight coefficients of a selected weight matrix and the corresponding feature values in each of the corresponding logic operation units according to the weight matrix information, and causes the logic operation units to perform computing operations parallelly to output intermediate layer feature values to an external processing unit.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A memory apparatus and an operation method thereof are provided. The memory apparatus includes a mode configuration register, a system memory array, a pointer and an arithmetic circuit including logic operation units. The mode configuration register stores weight matrix information and a base address. The system memory array stores feature values in a feature map from the base address according to the weight matrix information. The pointer stores the base address and a weight matrix size to provide pointer information. The arithmetic circuit sequentially or parallelly reads the feature values according to the pointer information. The arithmetic circuit parallelly arranges weight coefficients of a selected weight matrix and the corresponding feature values in each of the corresponding logic operation units according to the weight matrix information, and causes the logic operation units to perform computing operations parallelly to output intermediate layer feature values to an external processing unit.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path.

Abstract: A memory operation method applicable to a memory storage device is provided. The memory operation method including the following steps: receiving, from a memory controller, a first operation command for performing a first memory operation on a memory array of the memory storage device; and in response to the first operation command, transmitting first address information of the memory array corresponding to the first memory operation to the memory controller through a data interface of the memory storage device. In addition, a memory storage device using the memory operation method is also provided.

Abstract: A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path.

Abstract: A memory device is provided. The memory device includes a pseudo static random access memory (PSRAM), a word line (WL) arbitrator and a refresh controller. The WL arbitrator receives a WL signal and segments the WL signal according to a burst length setting value, to obtain a segmented WL signal. In a synchronous mode, the refresh controller provides a first refresh trigger signal corresponding to the WL signal to refresh the PSRAM. In a smart refresh mode, the refresh controller provides a second refresh trigger signal corresponding to the segmented WL signal to refresh the PSRAM.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A memory device is provided. The memory device includes a pseudo static random access memory (PSRAM), a word line (WL) arbitrator and a refresh controller. The WL arbitrator receives a WL signal and segments the WL signal according to a burst length setting value, to obtain a segmented WL signal. In a synchronous mode, the refresh controller provides a first refresh trigger signal corresponding to the WL signal to refresh the PSRAM. In a smart refresh mode, the refresh controller provides a second refresh trigger signal corresponding to the segmented WL signal to refresh the PSRAM.

Abstract: The present invention reveals an electrostatic discharge protection apparatus including a silicon controlled rectifier, a triggering voltage adapter network and a holding voltage adapter network. Additionally, the triggering voltage adapter network and the holding voltage adapter network are coupled to the silicon controlled rectifier. The present invention can change the characteristic of current vs. voltage by adjusting the triggering voltage and the holding voltage of the silicon controlled rectifier to meet the special requirement of various chips, and effectively prevent the chips from being damaged caused by the electrostatic discharging.

Abstract: The present invention reveals an electrostatic discharge protection apparatus including a silicon controlled rectifier, a triggering voltage adapter network and a holding voltage adapter network. Additionally, the triggering voltage adapter network and the holding voltage adapter network are coupled to the silicon controlled rectifier. The present invention can change the characteristic of current vs. voltage by adjusting the triggering voltage and the holding voltage of the silicon controlled rectifier to meet the special requirement of various chips, and effectively prevent the chips from being damaged caused by the electrostatic discharging.