Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: An antenna structure is provided, which includes a substrate, a horizontal radiator and a vertical radiator. The horizontal radiator is on or in the substrate. The vertical radiator is in the substrate and includes a vertical conductor, planar metal structures and a switch. The planar metal structures are electrically connected through the vertical conductor. The switch is in a gap of the planar metal structures and is coupled to at least one of the planar metal structures for switching a current distribution of the vertical radiator.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: An antenna structure is provided, which includes a substrate, a horizontal radiator and a vertical radiator. The horizontal radiator is on or in the substrate. The vertical radiator is in the substrate and includes a vertical conductor, planar metal structures and a switch. The planar metal structures are electrically connected through the vertical connector. The switch is in a gap of the planar metal structures and is coupled to at least one of the planar metal structures for switching a current distribution of the vertical radiator.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Abstract: An antenna structure is provided, which includes a substrate, a horizontal radiator and a vertical radiator. The horizontal radiator is on or in the substrate. The vertical radiator is in the substrate and includes a vertical conductor, planar metal structures and a switch. The planar metal structures are electrically connected through the vertical conductor. The switch is in a gap of the planar metal structures and is coupled to at least one of the planar metal structures for switching a current distribution of the vertical radiator.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

Abstract: A tracking system and a computer-implement operating method for the same are provided. The method includes transmitting a plurality of request wireless signals; in response to receiving the request wireless signals by the tag device, transmitting a plurality corresponding response wireless signals by the tag device; in response to receiving the corresponding response wireless signals by the anchor array, calculating a plurality of distances between the tag device and each of a plurality of anchor devices of the anchor array according to the request wireless signals and the response wireless signals, and accordingly calculating an absolute coordinate of the tag device; and in response to the absolute coordinate of the tag device is identified as being in a seen space of the virtual space by the processor, rendering a virtual object corresponding to the physical object into the seen space according to the absolute coordinate of the tag device.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Abstract: An integrated antenna structure is provided, which includes a substrate and a dual-polarized antenna unit disposed in the substrate and near a side edge of the substrate. The dual-polarized antenna unit includes a horizontally polarized antenna configured to generate a horizontally polarized beam and a vertically polarized antenna configured to generate a vertically polarized beam.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Abstract: An antenna structure includes a substrate, a vertical radiator, a reflective structure and a horizontal metal branch. The vertical radiator is in the substrate. The reflective structure is laterally disposed external to the vertical radiator. The horizontal metal branch is coupled to the reflective structure.

Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

Abstract: An antenna structure includes a substrate, a vertical radiator, a reflective structure and a horizontal metal branch. The vertical radiator is in the substrate. The reflective structure is laterally disposed external to the vertical radiator. The horizontal metal branch is coupled to the reflective structure.

Abstract: An antenna structure is provided, which includes a substrate, a horizontal radiator and a vertical radiator. The horizontal radiator is on or in the substrate. The vertical radiator is in the substrate and includes a vertical conductor, planar metal structures and a switch. The planar metal structures are electrically connected through the vertical connector. The switch is in a gap of the planar metal structures and is coupled to at least one of the planar metal structures for switching a current distribution of the vertical radiator.

Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n?1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.