Abstract: Provided is a tablet holder for clamping a tablet, including: a first U-groove coupling part provided with a first opening and a first accommodating portion, wherein the first U-groove coupling part is provided with a first clamping portion at one end and a first coupling opening at another end; a second U-groove coupling part provided with a second opening and a second accommodating portion, wherein the second U-groove coupling part is provided with a second clamping portion at one end and provided with a second coupling opening at another end; and a positioning member. The tablet is placed in a clamping space formed between the first clamping portion and the second clamping portion, the second U-groove coupling part and the first U-groove coupling part can slide relative to each other, and thus the tablet can be firmly clamped in the clamping space by an action of the positioning member.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A computing system performs balanced power management based on requirements of graphics scenes in a video game. Based on the requirements of the graphics scenes, the system selects one or more performance metrics to reduce in real-time, where the performance metrics are indicators of video game quality. The system compares estimated power consumption with a power budget after reducing the one or more performance metrics. Based on the requirements of the graphics scenes, the system further selects one or more quality enhancers to activate in real-time while keeping the estimated power consumption within the power budget. Each quality enhancer enhances the video game with respect to a performance metric. The system then displays the video game enhanced by the one or more quality enhancers.

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Abstract: A flash memory controller includes a specific buffer and a processor. The specific buffer allocates a cache space. The processor receives a specific host address sent from the host device, reads and loads a corresponding address pointer mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer linker, determines a specific address pointer corresponding to the specific host address from the corresponding address pointer mapping table according to the specific host address, reads and loads a corresponding address mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer corresponding to the specific host address, and finds a specific flash memory address from the corresponding address mapping table according to the specific host address to perform an access operation in response to the found specific flash memory address.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

Abstract: An electrical connector includes an outer shell, an insulating element, and a central conductive terminal. The outer shell includes a mounting hole. The insulating element is installed in the mounting hole. The central conductive terminal includes a first fitting portion, a second fitting portion and an intermediate portion. When a signal is transmitted in the first fitting portion, it encounters an impedance having a first impedance value. When the signal is transmitted in the second fitting portion, it encounters an impedance having a second impedance value. The intermediate portion includes an impedance transition area. When the signal is transmitted in the impedance transition area, it encounters an impedance having a gradually changing third impedance value. The first impedance value, the third impedance value and the second impedance value generally have a smooth transition. An adapter and a test device having the electrical connector are disclosed.

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

Abstract: In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.

Abstract: Disclosed herein are recombinant baculoviruses suitable for detecting the presence of arthropod-borne viruses in a biological sample of a test subject. The information derived from the detection may also be used to render a diagnosis on whether the test subject is infected with the arthropod-borne viruses or not, so that proper course of treatment may be assigned to the subject.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: Provided is a semiconductor device including an enhancement mode (E-mode) high electron mobility transistor (HEMT). The E-mode HEMT includes a substrate, and a channel layer disposed on the substrate. A barrier structure disposed on the channel layer. A pair of source/drain (S/D) metals respectively disposed on the channel layer at opposite sides of the barrier structure. A gate metal disposed on the barrier structure between the pair of S/D metals. The channel layer has a two-dimensional electron gas (2DEG) layer close to an interface between the channel layer and the barrier structure. A fluorine ion concentration in the channel layer adjacent to the 2DEG layer is greater than that away from the 2DEG layer.