Abstract: A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.

Abstract: A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.

Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.

Abstract: A chip package circuit board module including a circuit board and at least one original chip is provided. The circuit board includes at least one first pad, at least one second pad and at least one substitute pad. The at least one second pad is located besides the at least one first pad and separated from the at least one first pad. The at least one substitute pad is adjacent to the at least one second pad and separated from the at least one first pad and the at least one second pad. The at least one original chip is connected to the at least one first pad and at least one the second pad, respectively. A total width of a portion corresponding to each of the at least one second pad and a portion corresponding to the substitute pad adjacent to the second pad of the first pad is greater than or equal to twice a width of the original chip.

Abstract: A chip package circuit board module including a circuit board and at least one original chip is provided. The circuit board includes at least one first pad, at least one second pad and at least one substitute pad. The at least one second pad is located besides the at least one first pad and separated from the at least one first pad. The at least one substitute pad is adjacent to the at least one second pad and separated from the at least one first pad and the at least one second pad. The at least one original chip is connected to the at least one first pad and at least one the second pad, respectively. A total width of a portion corresponding to each of the at least one second pad and a portion corresponding to the substitute pad adjacent to the second pad of the first pad is greater than or equal to twice a width of the original chip.

Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A dicing process is performed, such that at least one slit is formed in the glass film. A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on the glass film. A polymer layer is formed on the first circuit layer. The polymer layer covers surfaces of the first circuit layer and the glass film. A plurality of second conductive vias are formed in the polymer layer. A second circuit layer is formed on the polymer layer, such that a first circuit board structure is formed. A singulation process is performed, such that the first circuit board structure is divided into a plurality of second circuit board structures.

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers a surface of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed.

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A dicing process is performed, such that at least one slit is formed in the glass film. A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on the glass film. A polymer layer is formed on the first circuit layer. The polymer layer covers surfaces of the first circuit layer and the glass film. A plurality of second conductive vias are formed in the polymer layer. A second circuit layer is formed on the polymer layer, such that a first circuit board structure is formed. A singulation process is performed, such that the first circuit board structure is divided into a plurality of second circuit board structures.

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers a surface of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed.