Patents by Inventor Chien-Tsu YEH

Chien-Tsu YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Signal converting circuit and bias voltage generation circuit thereof
    Patent number: 12334916
    Abstract: The present disclosure provides a signal converting circuit including a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert multiple input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal. The reference information is relevant to a change of the phase interpolator circuit due to a manufacture process variation.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: June 17, 2025
    Assignee: Realtek Semiconductor Corporation
    Inventors: Chien-Tsu Yeh, Hsi-En Liu, Yi-Chun Hsieh
  • Signal converting circuit
    Patent number: 12249979
    Abstract: A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: March 11, 2025
    Assignee: Realtek Semiconductor Corporation
    Inventors: Chien-Tsu Yeh, Hsi-En Liu, Yi-Chun Hsieh
  • SIGNAL CONVERTING CIRCUIT
    Publication number: 20230291397
    Abstract: A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 14, 2023
    Inventors: Chien-Tsu YEH, Hsi-En LIU, Yi-Chun HSIEH
  • SIGNAL CONVERTING CIRCUIT AND BIAS VOLTAGE GENERATION CIRCUIT THEREOF
    Publication number: 20230291398
    Abstract: The present disclosure provides a signal converting circuit including a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert multiple input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal. The reference information is relevant to a change of the phase interpolator circuit due to a manufacture process variation.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 14, 2023
    Inventors: Chien-Tsu YEH, Hsi-En LIU, Yi-Chun HSIEH