Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.

Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.

Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a static random access memory (SRAM) cell, a power-supply assist-voltage generator circuit, a source assist-voltage generator circuit, and a word-line assist-voltage generator circuit. The power-supply assist-voltage generator circuit, the source assist-voltage generator circuit, and the word-line assist-voltage generator circuit lower the effective supply voltage for un-accessed rows of memory cells in the hold mode, increase the effective supply voltage for accessed memory cells in the active mode, and lower the effective supply voltage further for all the SRAM cells in the standby mode to achieve a solution for active and standby power reduction besides achieving the stability and noise margins.

Abstract: A memory device and an operation method thereof is disclosed. The memory device includes a static random access memory (SRAM) cell, a power-supply assist-voltage generator circuit, a source assist-voltage generator circuit, and a word-line assist-voltage generator circuit. The power-supply assist-voltage generator circuit, the source assist-voltage generator circuit, and the word-line assist-voltage generator circuit lower the effective supply voltage for un-accessed rows of memory cells in the hold mode, increase the effective supply voltage for accessed memory cells in the active mode, and lower the effective supply voltage further for all the SRAM cells in the standby mode to achieve a solution for active and standby power reduction besides achieving the stability and noise margins.

Abstract: A single-ended sense amplifier includes a virtual-supply voltage-adapted (VVDD-adapted) inverter circuit, a virtual-supply voltage-adapted (VVDD-adapted) voltage-level converter circuit (VLC), and a virtual-supply-voltage-adaptation circuit (VSVA). The single-ended sense amplifier receives a data signal input, a sensing-operation-enabling signal input, and a pre-charging control signal input to generate a final amplified signal output. There are a first virtual-supply node and a second virtual-supply node in the VVDD-adapted inverter circuit. There is a third virtual-supply node in the VVDD-adapted VLC. The VSVA connects both the first and third virtual supply voltage nodes. The output end of the virtual-supply voltage-adapted inverter circuit connects to the input end of the VVDD-adapted VLC.