Abstract: An anti-warpage reinforced carrier includes a substrate, a plurality of rigid insulating plates, a plurality of metal posts, a resin layer, a first circuit layer, and a second circuit layer. The rigid insulating plates are arranged on the positioning areas on the substrate. The metal posts are in the second through holes penetrating through the rigid insulating plate. The resin layer covers the rigid insulating plates and the upper surface of the substrate, and includes a plurality of openings. The first circuit layer is on the resin layer and in the openings, and is connected to the metal posts. The second circuit layer is on a lower surface of the substrate and in the first through holes penetrating through the substrate, and is connected to the metal posts. By embedding rigid insulating plates therein, the anti-warpage reinforced carrier provides thermal stability, and is suitable for applications in advanced chip packaging.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: A chip package includes a semiconductor substrate, a light-transmissive plate, a bonding layer, and a light-shielding layer. The bonding layer is located between the semiconductor substrate and the light-transmissive plate. The semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall including a first region and a second region. The first region extends from the semiconductor substrate to the light-transmissive plate, and is recessed relative to the second region. The light-shielding layer covers the sidewall and includes an extending portion, a wide portion, and a narrow portion. The extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer. The wide portion is located on the first region of the sidewall. The narrow portion is located on the second region of the sidewall.

Abstract: A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: A semiconductor die includes a semiconductor device fabricated in a substrate. The substrate has a front side, a back side, and an inclined sidewall extending from the back side to the front side. A contact pad is connected to the semiconductor device. The contact pad is embedded in an inter dielectric layer (IDL) disposed in the front side. The contact pad has a contact pad edge with a surface aligned along the inclined sidewall. A redistribution layer (RDL) is disposed on the inclined sidewall. The RDL is physically and electrically connected to the contact pad directly through the surface of the contact pad edge aligned along the inclined sidewall.

Abstract: A package includes an optical sensor die. The optical sensor die has an optically active surface area (OASA) disposed on a front side of a substrate. A glass cover is disposed above the OASA and attached to the front side the substrate by a dam material. A through-substrate via (TSV) extends from an opening at a back side of the substrate toward a front side of the substrate. The TSV has a stepped bottom surface at the front side of the substrate. The TSV provides access for electrical connections between the back side of the substrate and the front side of the substrate.

Abstract: In some embodiments, the present disclosure relates to a chemical mechanical planarization (CMP) tool. The CMP tool includes a carrier and a malleable membrane coupled to the carrier and having a lower surface facing away from the carrier. The lower surface of the malleable membrane includes a first malleable material within a central region of the lower surface and a second malleable material within a peripheral region of the lower surface, which surrounds the central region. The first malleable material provides the central region of the lower surface with a first stiffness and the second malleable material provides the peripheral region of the lower surface with a second stiffness that is different than the first stiffness.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.

Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.

Abstract: In some embodiments, the present disclosure relates to a chemical mechanical planarization (CMP) tool. The CMP tool includes a carrier and a malleable membrane coupled to the carrier and having a lower surface facing away from the carrier. The lower surface of the malleable membrane includes a first malleable material within a central region of the lower surface and a second malleable material within a peripheral region of the lower surface, which surrounds the central region. The first malleable material provides the central region of the lower surface with a first stiffness and the second malleable material provides the peripheral region of the lower surface with a second stiffness that is different than the first stiffness.

Abstract: In some embodiments, the present disclosure, in some embodiments, relates to a method of forming a CMP membrane. The method is performed by providing a malleable material within a cavity within a membrane mold. The cavity has a central region and a peripheral region surrounding the central region. The malleable material within the cavity is cured to form a membrane. Curing the malleable material is performed by heating the malleable material within the central region of the membrane mold to a first temperature and heating the malleable material within the peripheral region of the membrane mold to a second temperature that is greater than the first temperature.

Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: In some embodiments, the present disclosure, in some embodiments, relates to a method of forming a CMP membrane. The method is performed by providing a malleable material within a cavity within a membrane mold. The cavity has a central region and a peripheral region surrounding the central region. The malleable material within the cavity is cured to form a membrane. Curing the malleable material is performed by heating the malleable material within the central region of the membrane mold to a first temperature and heating the malleable material within the peripheral region of the membrane mold to a second temperature that is greater than the first temperature.