Abstract: Techniques for facilitating natural language interactions with visual interactive content are described. During a build time, a system analyzes various websites and applications relating to a particular user goal to understand website and application navigation and information relating to the user goal. The learned information is used to store configuration data. During runtime, when a user request performance of an action, the system engages in a dialog with the user to complete the user's goal. The system uses the stored configuration data to determine actions to be performed at a website or application to complete the user's goal, and determines system responses to present to the user to facilitate completion of the goal. Such system responses may request information from the user, may inform the user of information displayed at the website or application, etc.

Abstract: Techniques for facilitating natural language interactions with visual interactive content are described. During a build time, a system analyzes various websites and applications relating to a particular user goal to understand website and application navigation and information relating to the user goal. The learned information is used to store configuration data. During runtime, when a user request performance of an action, the system engages in a dialog with the user to complete the user's goal. The system uses the stored configuration data to determine actions to be performed at a website or application to complete the user's goal, and determines system responses to present to the user to facilitate completion of the goal. Such system responses may request information from the user, may inform the user of information displayed at the website or application, etc.

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

Abstract: A video decoder has a plurality of processing circuits, including a first processing circuit and a second processing circuit. The first processing circuit applies a first decoding process to a current coding block according to reconstructed neighbor samples, and has a local neighbor buffer for buffering the reconstructed neighbor samples used by the first decoding process. The second processing circuit applies a second decoding process to the current coding block according to at least a portion of the reconstructed neighbor samples retrieved from the local neighbor buffer, wherein the second decoding process is different from the first decoding process.

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

Abstract: A carrier system that includes a nanocarrier and a peptide non-covalently associated with the nanocarrier. The peptide contains an adaptor peptide sequence fused to the N-terminus of a target peptide, the adaptor peptide sequence being designed to facilitate the association to the nanocarrier. Also disclosed is a method for improving the immunogenicity of a peptide antigen by fusing it to an adaptor peptide sequence to form an immunizing peptide and contacting the immunizing peptide with a compatible nanocarrier. Further, a method is provided for treating a condition by immunization with a target peptide that has been fused to an adaptor peptide sequence and thereby associated with a nanocarrier. The method induces an immune response against the target peptide for treating cancer, viral infection, bacterial infection, parasitic infection, autoimmunity, or undesired immune responses to a biologies treatment.

Abstract: A dialog generator receives data corresponding to desired dialog, such as application programming interface (API) information and sample dialog. A first model corresponding to an agent simulator and a second model corresponding to a user simulator take turns creating a plurality of dialog outlines of the desired dialog. The dialog generator may determine that one or more additional APIs are relevant to the dialog and may create further dialog outlines related thereto. The dialog outlines are converted to natural dialog to generate the dialog.

Abstract: The present disclosure provides a stacked-type solid electrolytic capacitor package structure and a method of manufacturing the same. The capacitor package structure includes a capacitor unit, a solder unit, a package unit and a conductive unit. The capacitor unit includes a plurality of first stacked capacitors. Each first stacked capacitor includes a first positive portion and a first negative portion. The first positive portion has at least one first through hole. The first through holes of the first positive portions are in communication with each other to form a first communication hole. The solder unit includes a first connection solder for filling the first communication hole so as to connect the first positive portions with each other. The package unit includes a package body for enclosing the capacitor unit and the solder unit. The conductive unit includes a first conductive terminal and a second conductive terminal.

Abstract: The instant disclosure relates to a stacked-type solid electrolytic capacitor capable of increasing welding effect and a manufacturing method of the same. The stacked-type solid electrolytic capacitor includes a plurality of solid electrolytic capacitor units, each of which has an anode part and a cathode part connected to the anode part, characterized in that the anode part is formed with at least one buffering via-hole in a welding area thereof. When each of the anode parts is compressed in a welding process, the volume of the corresponding buffering via-hole decreases accordingly. Therefore, the soldering performance of the anode part solid electrolytic capacitor is enhanced and the connection stability is increased.

Abstract: The present disclosure provides a stacked-type solid electrolytic capacitor package structure and a method of manufacturing the same. The capacitor package structure includes a capacitor unit, a solder unit, a package unit and a conductive unit. The capacitor unit includes a plurality of first stacked capacitors. Each first stacked capacitor includes a first positive portion and a first negative portion. The first positive portion has at least one first through hole. The first through holes of the first positive portions are in communication with each other to form a first communication hole. The solder unit includes a first connection solder for filling the first communication hole so as to connect the first positive portions with each other. The package unit includes a package body for enclosing the capacitor unit and the solder unit. The conductive unit includes a first conductive terminal and a second conductive terminal.

Abstract: The instant disclosure relates to a stacked-type solid electrolytic capacitor capable of increasing welding effect and a manufacturing method of the same. The stacked-type solid electrolytic capacitor includes a plurality of solid electrolytic capacitor units, each of which has an anode part and a cathode part connected to the anode part, characterized in that the anode part is formed with at least one buffering via-hole in a welding area thereof. When each of the anode parts is compressed in a welding process, the volume of the corresponding buffering via-hole decreases accordingly. Therefore, the soldering performance of the anode part solid electrolytic capacitor is enhanced and the connection stability is increased.

Abstract: The present invention relates to a capacitor unit, which includes an anode portion, a cathode portion, and an insulating portion. The insulating portion is provided for in a form of a headband to partially cover the surface of the anode portion to divide the anode and the cathode portions. The cathode portion partially covers the anode portion and is located behind the insulating portion. The cathode portion has at least one conductive layer which is made of a conductive polymer having copper, copper alloy, or a mixture thereof.

Abstract: A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths.

Abstract: A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths.