Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue disposed in the peripheral region and overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue extends along an extension direction parallel to the first edge, and along the extension direction, a sum of lengths of the first conductive glue and the second conductive glue is less than a length of the insulating glue.

Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge and a second edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue is disposed in the peripheral region and extends along an extension direction parallel to the first edge, and along the extension direction, a first distance between the first conductive glue and the second edge is greater than a second distance between the second conductive glue and the second edge.

Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge and a second edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue is disposed in the peripheral region and extends along an extension direction parallel to the first edge, and along the extension direction, a first distance between the first conductive glue and the second edge is greater than a second distance between the second conductive glue and the second edge.

Abstract: A deployment system for IoT including an edge server, multiple gateways, and multiple agent modules is disclosed. Each gateway is respectively connected with different peripheral devices to support different function. The edge server includes a flow editor used to edit a flow for a target gateway. The edge server performs a deploying procedure to the target gateway in accordance with the flow, wherein the deploying procedure is to first read a script and a parameter of one or more function nodes included in the flow, then encapsulate the script and the parameter into a packet, and then transmit the packet to the target gateway through one of the agent modules. The target gateway receives the packet through one of the agent modules and sequentially executes the function nodes according to the content of the flow, so as to implement a corresponding IoT function.

Abstract: A deployment system for IoT including an edge server, multiple gateways, and multiple agent modules is disclosed. Each gateway is respectively connected with different peripheral devices to support different function. The edge server includes a flow editor used to edit a flow for a target gateway. The edge server performs a deploying procedure to the target gateway in accordance with the flow, wherein the deploying procedure is to first read a script and a parameter of one or more function nodes included in the flow, then encapsulate the script and the parameter into a packet, and then transmit the packet to the target gateway through one of the agent modules. The target gateway receives the packet through one of the agent modules and sequentially executes the function nodes according to the content of the flow, so as to implement a corresponding IoT function.

Abstract: A method for a CPU to execute artificial intelligence related processes is disclosed. The method includes: when executing TensorFlow on an electronic device, calling a corresponding AI model of TensorFlow according to content of program codes; determining and obtaining one or multiple sparse matrixes used by the AI model in performing calculations; executing a matrix simplifying procedure to the one or multiple sparse matrixes; executing an instruction transforming procedure to an instruction set applied for the AI model; issuing an instruction to a weighted CPU of the electronic device by the AI model according to transformed instruction set; and the weighted CPU, after receiving the instruction, averagely distributing multiple procedures indicated by the AI model to each of multiple threads of the weighted CPU to be respectively executed according to a weighting value of each of the multiple procedures.

Abstract: An electronic device includes a first substrate; a second substrate arranged opposite to the first substrate; a first electrode layer disposed on the first substrate; a display medium layer disposed between the first electrode layer and the second substrate; and a first metal element, wherein the first metal element is fixed on the first electrode layer through a conductive glue and an insulating glue; wherein in a normal direction of the first substrate, the conductive glue and the insulating glue are overlapped.

Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

Abstract: An electronic device includes a first substrate; a second substrate arranged opposite to the first substrate; a first electrode layer disposed on the first substrate; a display medium layer disposed between the first electrode layer and the second substrate; and a first metal element, wherein the first metal element is fixed on the first electrode layer through a conductive glue and an insulating glue; wherein in a normal direction of the first substrate, the conductive glue and the insulating glue are overlapped.

Abstract: An electronic device includes a first substrate; a second substrate arranged opposite to the first substrate; a first electrode layer disposed on the first substrate; a second electrode layer disposed on the second substrate; a display medium layer disposed between the first electrode layer and the second electrode layer; a sealant disposed between the first electrode layer and the second electrode layer to surround the display medium layer; and a first metal element extending along a first direction, wherein the first metal element is fixed onto the first electrode layer through a conductive glue and a first insulating glue.

Abstract: A method for a CPU to execute artificial intelligence related processes is disclosed. The method includes: when executing TensorFlow on an electronic device, calling a corresponding AI model of TensorFlow according to content of program codes; determining and obtaining one or multiple sparse matrixes used by the AI model in performing calculations; executing a matrix simplifying procedure to the one or multiple sparse matrixes; executing an instruction transforming procedure to an instruction set applied for the AI model; issuing an instruction to a weighted CPU of the electronic device by the AI model according to transformed instruction set; and the weighted CPU, after receiving the instruction, averagely distributing multiple procedures indicated by the AI model to each of multiple threads of the weighted CPU to be respectively executed according to a weighting value of each of the multiple procedures.

Abstract: An electronic device includes a first substrate; a second substrate arranged opposite to the first substrate; a first electrode layer disposed on the first substrate; a second electrode layer disposed on the second substrate; a display medium layer disposed between the first electrode layer and the second electrode layer; a sealant disposed between the first electrode layer and the second electrode layer to surround the display medium layer; and a first metal element extending along a first direction, wherein the first metal element is fixed onto the first electrode layer through a conductive glue and a first insulating glue.

Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

Abstract: A quadrature transmitter includes a first and second matched transmitter path. Each transmitter path receives respective sets of quadrature baseband signals. At least one local oscillator port receives respective sets of quadrature LO signals. Mixer stage(s) respectively multiply the sets of quadrature baseband signals with the respective sets of quadrature LO signals to produce a respective output radio frequency signal. A combiner combines the output RF signals. The first set of quadrature signals is a substantially 45° phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45° phase shifted version of the second set of quadrature LO signals. A baseband error correction circuit corrects a phase error between the quadrature baseband signals at baseband and a LO error correction circuit corrects a phase error between the quadrature baseband signals at a LO frequency.

Abstract: A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

Abstract: A quadrature transmitter includes a first and second matched transmitter path. Each transmitter path receives respective sets of quadrature baseband signals. At least one local oscillator port receives respective sets of quadrature LO signals. Mixer stage(s) respectively multiply the sets of quadrature baseband signals with the respective sets of quadrature LO signals to produce a respective output radio frequency signal. A combiner combines the output RF signals. The first set of quadrature signals is a substantially 45° phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45° phase shifted version of the second set of quadrature LO signals. A baseband error correction circuit corrects a phase error between the quadrature baseband signals at baseband and a LO error correction circuit corrects a phase error between the quadrature baseband signals at a LO frequency.

Abstract: A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.

Abstract: A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier.

Abstract: A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path.

Abstract: A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path.