Patents by Inventor Chien-Wen Chu
Chien-Wen Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9691874Abstract: A manufacturing method of a semiconductor structure provides a substrate. A well having a first conductive type and a well having a second conductive type are formed in the substrate, respectively. A body region is formed in the well having the second conductive type. A first doped region and a second doped region are formed in the well having the first conductive type and the body region respectively. The first and second doped regions have same polarities, and a dopant concentration of the second doped region is higher than that of the first doped region. A third doped region is formed in the well having the second conductive type and between the first and second doped regions. The third and first doped regions have reverse polarities. A first field plate is formed on a surface region between the second and third doped regions.Type: GrantFiled: March 9, 2015Date of Patent: June 27, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Publication number: 20150179754Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.Type: ApplicationFiled: March 9, 2015Publication date: June 25, 2015Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Patent number: 9064955Abstract: A semiconductor device includes a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.Type: GrantFiled: November 11, 2013Date of Patent: June 23, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
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Patent number: 9029952Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.Type: GrantFiled: April 19, 2012Date of Patent: May 12, 2015Assignee: Macronix International Co., Ltd.Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Patent number: 9029950Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.Type: GrantFiled: March 20, 2012Date of Patent: May 12, 2015Assignee: Macronix International Co., Ltd.Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
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Patent number: 8716825Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is on the well region. The dielectric structure has a first dielectric sidewall and a second dielectric sidewall opposite to each other. The dielectric structure includes a first dielectric portion and a second dielectric portion, between the first dielectric sidewall and the second dielectric sidewall. The first doped layer is on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is in the well region on the first dielectric sidewall.Type: GrantFiled: June 22, 2011Date of Patent: May 6, 2014Assignee: Macronix International Co., Ltd.Inventors: Wing-Chor Chan, Chung-Yu Hung, Chien-Wen Chu
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Patent number: 8669639Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.Type: GrantFiled: June 11, 2012Date of Patent: March 11, 2014Assignee: Macronix International Co., Ltd.Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Publication number: 20140061790Abstract: A semiconductor device includes a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.Type: ApplicationFiled: November 11, 2013Publication date: March 6, 2014Inventors: Chien-Wen CHU, Wing-Chor CHAN, Shyi-Yuan WU
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Patent number: 8610206Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.Type: GrantFiled: February 18, 2011Date of Patent: December 17, 2013Assignee: Macronix International Co., Ltd.Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
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Publication number: 20130328170Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Publication number: 20130277805Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.Type: ApplicationFiled: April 19, 2012Publication date: October 24, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Publication number: 20130249007Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
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Patent number: 8525261Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region.Type: GrantFiled: November 23, 2010Date of Patent: September 3, 2013Assignee: Macronix International Co., Ltd.Inventors: Shyi-Yuan Wu, Wing Chor Chan, Chien-Wen Chu
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Patent number: 8482066Abstract: A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion.Type: GrantFiled: September 2, 2011Date of Patent: July 9, 2013Assignee: Macronix International Co., Ltd.Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
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Publication number: 20130056824Abstract: A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion.Type: ApplicationFiled: September 2, 2011Publication date: March 7, 2013Applicant: Macronix International Co., Ltd.Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
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Patent number: 8362558Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.Type: GrantFiled: May 4, 2011Date of Patent: January 29, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Hsueh-I Huang, Chien-Wen Chu, Cheng-Chi Lin, Shih-Chin Lien, Chin-Pen Yeh, Shyi-Yuan Wu
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Publication number: 20120326261Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is on the well region. The dielectric structure has a first dielectric sidewall and a second dielectric sidewall opposite to each other. The dielectric structure includes a first dielectric portion and a second dielectric portion, between the first dielectric sidewall and the second dielectric sidewall. The first doped layer is on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is in the well region on the first dielectric sidewall.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wing-Chor Chan, Chung-Yu Hung, Chien-Wen Chu
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Publication number: 20120211832Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.Type: ApplicationFiled: February 18, 2011Publication date: August 23, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Wen CHU, Wing-Chor CHAN, Shyi-Yuan WU
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Publication number: 20120126323Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shyi-Yuan Wu, Wing Chor Chan, Chien-Wen Chu
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Publication number: 20120104492Abstract: The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chien-Wen CHU, Wing-Chor CHAN, Shyi-Yuan WU