Patents by Inventor Chien-Wen Yu
Chien-Wen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12283637Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: GrantFiled: October 31, 2022Date of Patent: April 22, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Publication number: 20240413233Abstract: A GaN-based semiconductor device includes a substrate; a GaN channel layer disposed on the substrate; a AlGaN layer disposed on the GaN channel layer; a p-GaN gate layer disposed on the AlGaN layer; and a nitrogen-rich TiN hard mask layer disposed on the p-GaN gate layer. The nitrogen-rich TiN hard mask layer has a nitrogen-to-titanium (N/Ti) ratio that is greater than 1.0. A gate electrode layer is disposed on the nitrogen-rich TiN hard mask layer.Type: ApplicationFiled: July 13, 2023Publication date: December 12, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chuan Chen, Po-Wei Wang, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20240243185Abstract: Provided is a semiconductor device including an enhancement mode (E-mode) high electron mobility transistor (HEMT). The E-mode HEMT includes a substrate, and a channel layer disposed on the substrate. A barrier structure disposed on the channel layer. A pair of source/drain (S/D) metals respectively disposed on the channel layer at opposite sides of the barrier structure. A gate metal disposed on the barrier structure between the pair of S/D metals. The channel layer has a two-dimensional electron gas (2DEG) layer close to an interface between the channel layer and the barrier structure. A fluorine ion concentration in the channel layer adjacent to the 2DEG layer is greater than that away from the 2DEG layer.Type: ApplicationFiled: February 17, 2023Publication date: July 18, 2024Applicant: United Microelectronics Corp.Inventors: Huan Chi Ma, Kuan-Ting Lin, Ying Jie Huang, Chien-Wen Yu
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Publication number: 20240175771Abstract: Embodiments of the disclosure provide a method and device for providing a wire breakage warning. The method includes: obtaining a plurality of process values when a crystal ingot cutting machine uses a cutting wire to cut a crystal ingot; dividing the process values into N groups, and determining a statistical property of each of the groups; identifying outlier values in the process values based on the statistical property of each of the groups, or determining a statistical property variation corresponding to each of the groups based on the statistical property of each of the groups; and in response to determining that the outlier values in the process values meet a first warning condition, or the statistical property variation corresponding to each of the groups meets a second warning condition, providing a wire breakage warning associated with the cutting wire.Type: ApplicationFiled: November 30, 2022Publication date: May 30, 2024Applicant: GlobalWafers Co., Ltd.Inventors: Chien-Wen YU, Shang-Chi Wang, Bo-Ting Lin
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Patent number: 11916126Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.Type: GrantFiled: November 18, 2022Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
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Patent number: 11664425Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: GrantFiled: January 20, 2022Date of Patent: May 30, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20230078993Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.Type: ApplicationFiled: November 18, 2022Publication date: March 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
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Publication number: 20230048684Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Patent number: 11538917Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.Type: GrantFiled: June 22, 2021Date of Patent: December 27, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
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Publication number: 20220384603Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.Type: ApplicationFiled: June 22, 2021Publication date: December 1, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
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Publication number: 20220181505Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: January 11, 2021Publication date: June 9, 2022Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Publication number: 20220140080Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: ApplicationFiled: January 20, 2022Publication date: May 5, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 11271078Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: GrantFiled: April 1, 2020Date of Patent: March 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20200235208Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: ApplicationFiled: April 1, 2020Publication date: July 23, 2020Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 10651275Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: GrantFiled: February 11, 2018Date of Patent: May 12, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 10388788Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa.Type: GrantFiled: June 28, 2017Date of Patent: August 20, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu, Kuo-Chin Hung
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Publication number: 20190214465Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: ApplicationFiled: February 11, 2018Publication date: July 11, 2019Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20180342618Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET.Type: ApplicationFiled: June 28, 2017Publication date: November 29, 2018Inventors: Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu, Kuo-Chin Hung
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Publication number: 20080036741Abstract: A hand-held device capable of controlling a keyboard-video-mouse switch and method thereof is disclosed. The hand-held device shows a control menu for inputting a control signal to control the keyboard-video-mouse switch or particularly an on screen display circuit of the keyboard-video-mouse switch. The keyboard-video-mouse switch includes a processor and a second interface. The hand-held device includes a menu generator, a user interface and a first interface. The menu generator generates a control menu. The user interface shows the control menu for inputting a control signal into the hand-held device. The first interface transmits the control signal to the second interface of the keyboard-video-mouse switch. The keyboard-video-mouse switch receives the control signal via the second interface. The second interface transmits a response signal of the control signal from the processor of the keyboard-video-mouse switch to the hand-held device via the first interface.Type: ApplicationFiled: August 11, 2006Publication date: February 14, 2008Applicant: Aten International Co., Ltd.Inventors: Chih-Tao Hsieh, Chien-Wen Yu
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Publication number: 20080030331Abstract: An anti-thief electronic device capable of confirming respective existing statuses of a plurality of apparatuses coupled thereto and method thereof is disclosed. The anti-thief electronic device includes a first table, a second table, a micro control unit and an alert device. The first table stores respective initial existing statuses of the apparatuses coupled to the anti-thief electronic device as regular existing statuses. The second table stores respective existing statuses of the apparatuses periodically. The micro control unit periodically compares the second table with the first table to confirm whether the respective existing statuses of the apparatuses are changed or not. The alert device generates an alert if the respective existing statuses of the apparatuses are changed. Specifically, the micro control unit periodically queries an extended display identification data from the display for detecting the removal of the display.Type: ApplicationFiled: August 4, 2006Publication date: February 7, 2008Applicant: Aten International Co., Ltd.Inventors: Sun-chung Chen, Shih-yuan Huang, Chein-chung Chen, Chien-wen Yu