Patents by Inventor Chien-Yeh Liu

Chien-Yeh Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157855
    Abstract: The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package includes a carrier, at least one electronic component, a first magnetic layer and a second magnetic layer. The carrier has a top surface on which the electronic component is disposed. The first magnetic layer is disposed on the top surface of the carrier and encapsulates the electronic component. The second magnetic layer is disposed on the first magnetic layer and covers a top surface and a lateral surface of the first magnetic layer. A permeability of the first magnetic layer is less than a permeability of the second magnetic layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: December 18, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Hsuan Lee, Chien-Yeh Liu, Sung-Mao Li, Jaw-Ming Ding
  • Patent number: 9653415
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of electronic components, a first package body, a patterned conductive layer and a feeding element. The semiconductor device and the plurality of electronic components are disposed on the substrate. The first package body covers the semiconductor device but exposes the plurality of electronic components. The patterned conductive layer is formed on the first package body. The feeding element electrically connects the patterned conductive layer to the plurality of electronic components.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: May 16, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Hsuan Lee, Sung-Mao Li, Chien-Yeh Liu
  • Publication number: 20160358862
    Abstract: The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package includes a carrier, at least one electronic component, a first magnetic layer and a second magnetic layer. The carrier has a top surface on which the electronic component is disposed. The first magnetic layer is disposed on the top surface of the carrier and encapsulates the electronic component. The second magnetic layer is disposed on the first magnetic layer and covers a top surface and a lateral surface of the first magnetic layer. A permeability of the first magnetic layer is less than a permeability of the second magnetic layer.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 8, 2016
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Hsuan Lee, Chien-Yeh Liu, Sung-Mao Li, Jaw-Ming Ding
  • Publication number: 20160240493
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of electronic components, a first package body, a patterned conductive layer and a feeding element. The semiconductor device and the plurality of electronic components are disposed on the substrate. The first package body covers the semiconductor device but exposes the plurality of electronic components. The patterned conductive layer is formed on the first package body. The feeding element electrically connects the patterned conductive layer to the plurality of electronic components.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 18, 2016
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Hsuan LEE, Sung-Mao LI, Chien-Yeh LIU
  • Patent number: 9397074
    Abstract: A semiconductor package includes a substrate, a set of electrical components, a stud, a tapering electrical interconnection and a package body. The electrical components are disposed on a top surface of the substrate. A bottom surface of the stud is disposed on the top surface of the substrate. A bottom surface of the electrical interconnection is disposed at a top surface of the stud. A width of the stud is greater than or equal to a width of the bottom surface of the electrical interconnection. The package body is disposed on the top surface of the substrate, and encapsulates the electrical components, the stud and a portion of the electrical interconnection. The package body exposes a top surface of the electrical interconnection.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: July 19, 2016
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Hsuan Lee, Sung-Mao Li, Chien-Yeh Liu
  • Patent number: 9166530
    Abstract: A low noise amplifier is disclosed. The low noise amplifier comprises a current mirror circuit, a bias circuit, a cascode amplifying circuit and a power gain compensating circuit. The current mirror circuit is used for providing a mapping current. The bias circuit is used for receiving a mapping current and outputting a first bias voltage and a second bias voltage according to the mapping current. The cascode amplifying circuit respectively receives the first bias voltage and the second bias voltage, and accordingly to work at an operation bias point. The power gain compensating circuit is used for receiving a RF output signal and accordingly outputs a gain compensating signal to the current mirror circuit so as to dynamically adjust current value of the mapping current and further to compensates power gain of the low noise amplifier in order to increase linearity.
    Type: Grant
    Filed: March 16, 2014
    Date of Patent: October 20, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Jaw-Ming Ding, Chien-Yeh Liu
  • Patent number: 9148097
    Abstract: A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a first system voltage and provides a working voltage accordingly. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit detects a RF input signal and outputs a compensation voltage to the bias circuit according to variation of the RF input signal, wherein the dynamic bias controlling circuit is an open loop configuration. When an input power of the RF input signal increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover or enhance the operation bias point according to the compensation voltage received.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: September 29, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Jaw-Ming Ding, Chien-Yeh Liu
  • Publication number: 20150263675
    Abstract: A low noise amplifier is disclosed. The low noise amplifier comprises a current mirror circuit, a bias circuit, a cascode amplifying circuit and a power gain compensating circuit. The current mirror circuit is used for providing a mapping current. The bias circuit is used for receiving a mapping current and outputting a first bias voltage and a second bias voltage according to the mapping current. The cascode amplifying circuit respectively receives the first bias voltage and the second bias voltage, and accordingly to work at an operation bias point. The power gain compensating circuit is used for receiving a RF output signal and accordingly outputs a gain compensating signal to the current mirror circuit so as to dynamically adjust current value of the mapping current and further to compensates power gain of the low noise amplifier in order to increase linearity.
    Type: Application
    Filed: March 16, 2014
    Publication date: September 17, 2015
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: JAW-MING DING, CHIEN-YEH LIU
  • Patent number: 9123981
    Abstract: A tunable radio frequency (RF) coupler and manufacturing method thereof are provided. The tunable RF coupler includes an insulating layer, a first transmission line and a second transmission line. The second transmission line is disposed corresponding to the first transmission line and the insulating layer is disposed between the first transmission line and the second transmission line. The second transmission line includes a plurality of segments separated from each other and arranged along the extension path of the first transmission line. At least one wire is configured to establish an electrical connection between at least two segments, such that the two segments are electrically conductive to each other through the wire.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 1, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Chien-Yeh Liu, Wei-Hsuan Lee, Jaw-Ming Ding, Huang-Hua Wen
  • Publication number: 20150244053
    Abstract: A tunable radio frequency (RF) coupler and manufacturing method thereof are provided. The tunable RF coupler includes an insulating layer, a first transmission line and a second transmission line. The second transmission line is disposed corresponding to the first transmission line and the insulating layer is disposed between the first transmission line and the second transmission line. The second transmission line includes a plurality of segments separated from each other and arranged along the extension path of the first transmission line. At least one wire is configured to establish an electrical connection between at least two segments, such that the two segments are electrically conductive to each other through the wire.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 27, 2015
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: CHIEN-YEH LIU, Wei-Hsuan Lee, JAW-MING DING, Huang-Hua Wen
  • Patent number: 9024689
    Abstract: A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a system voltage and the bias circuit provides a working voltage according to the system voltage. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit receives the working voltage and outputs a compensation voltage to the bias circuit according to a variation of the working voltage. When the input power increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover the operation bias point according to the compensation voltage received.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: May 5, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Jaw-Ming Ding, Chien-Yeh Liu
  • Publication number: 20140191806
    Abstract: A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a first system voltage and provides a working voltage accordingly. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit detects a RF input signal and outputs a compensation voltage to the bias circuit according to variation of the RF input signal, wherein the dynamic bias controlling circuit is an open loop configuration. When an input power of the RF input signal increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover or enhance the operation bias point according to the compensation voltage received.
    Type: Application
    Filed: December 6, 2013
    Publication date: July 10, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: JAW-MING DING, CHIEN-YEH LIU
  • Patent number: 8766654
    Abstract: A package structure with conformal shielding includes a substrate providing electrically connected inner grounding structures, a chip module mounted on the substrate, a molding compound covering the chip module and one surface of the substrate, and a conductive shielding layer covering the molding compound and the lateral sides of the substrate, and electrically connected with a part of the inner grounding structures. The substrate further provides one or multiple independent conductive structures electrically connected with the conductive shielding layer and exposed to the outside. By measuring the resistance value between one independent conductive structure and the conductive shielding layer or another independent conductive structure or one ground contact and then comparing the measured resistance value with a predetermined reference value, the EMI shielding performance of the package structure is determined.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: July 1, 2014
    Assignees: Universal Scientific Industrial Co., Ltd., Universal Global Scientific Industrial Co., Ltd.
    Inventors: Jaw-Ming Ding, Chien-Yeh Liu, Chih-Hao Chiang
  • Publication number: 20140167854
    Abstract: A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a system voltage and the bias circuit provides a working voltage according to the system voltage. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit receives the working voltage and outputs a compensation voltage to the bias circuit according to a variation of the working voltage. When the input power increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover the operation bias point according to the compensation voltage received.
    Type: Application
    Filed: November 19, 2013
    Publication date: June 19, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: JAW-MING DING, CHIEN-YEH LIU
  • Publication number: 20130257462
    Abstract: A package structure with conformal shielding includes a substrate providing electrically connected inner grounding structures, a chip module mounted on the substrate, a molding compound covering the chip module and one surface of the substrate, and a conductive shielding layer covering the molding compound and the lateral sides of the substrate, and electrically connected with a part of the inner grounding structures. The substrate further provides one or multiple independent conductive structures electrically connected with the conductive shielding layer and exposed to the outside. By measuring the resistance value between one independent conductive structure and the conductive shielding layer or another independent conductive structure or one ground contact and then comparing the measured resistance value with a predetermined reference value, the EMI shielding performance of the package structure is determined.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicants: UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD., UNIVERSAL SCIENTIFIC INDUSTRIAL CO., LTD.
    Inventors: Jaw-Ming DING, Chien-Yeh Liu, Chih-Hao Chiang