Patents by Inventor Chien-Yu Hsieh

Chien-Yu Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133737
    Abstract: The present disclosure provides a test system and method. The test system is configured to analyze a system platform and includes a data collector and a test monitor. The data collector is configured to receive a signal transmitted between a controller and a memory of the system platform and is configured to process the signal to generate a processed signal. The test monitor is configured to encode the processed signal into a log information, so as to determine an operation status of the system platform according to the log information.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Chien Yu CHEN, Meng-Kai HSIEH
  • Publication number: 20240128955
    Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.
    Type: Application
    Filed: April 24, 2023
    Publication date: April 18, 2024
    Inventors: Shao-Yu Steve Wang, Chien-Te Wu, Shang-Chih Hsieh, Nick Tsai
  • Publication number: 20240118964
    Abstract: A fault analysis device and a fault analysis method of the fault analysis device are provided. A sensing circuit senses a first distorted signal on a first signal transmission path of an abnormal signal device when the abnormal signal device performs a preset operation. A signal generating circuit provides a fault test signal to a second signal transmission path of a standard device corresponding to the first signal transmission path when the standard device performs the preset operation, so as to generate a second distorted signal on the second signal transmission path, where the first distorted signal and the second distorted signal have the same signal distortion characteristics.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 11, 2024
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien Yu Chen, Meng-Kai Hsieh
  • Patent number: 11143675
    Abstract: An insulator applied in a probe base including a probe mounting hole, the insulator is a sheet structure having plural through holes, and the probe mounting hole is formed at the center of the insulator, and the probe mounting hole and the through hole penetrate from a first surface to a second surface of the insulator, and the regions of the first and second surfaces without the probe mounting hole and the through hole are coplanar. The probe base has a base body and at least a composite assembly, and the base body has at least a testing zone, and the composite assembly is installed in the testing zone and has at least a probe hole for installing a probe, and the insulator is installed into the probe hole.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 12, 2021
    Assignee: C.C.P. CONTACT PROBES CO., LTD.
    Inventors: Chien-Yu Hsieh, Yen-Chun Chen, Chih-Hui Hou, Wei-Chu Chen, Yen-Hui Lu, Ting-Chen Pan, Yen-Wei Lin, Bor-Chen Tsai
  • Publication number: 20190317129
    Abstract: An insulator applied in a probe base including a probe mounting hole, the insulator is a sheet structure having plural through holes, and the probe mounting hole is formed at the center of the insulator, and the probe mounting hole and the through hole penetrate from a first surface to a second surface of the insulator, and the regions of the first and second surfaces without the probe mounting hole and the through hole are coplanar. The probe base has a base body and at least a composite assembly, and the base body has at least a testing zone, and the composite assembly is installed in the testing zone and has at least a probe hole for installing a probe, and the insulator is installed into the probe hole.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 17, 2019
    Inventors: CHIEN-YU HSIEH, YEN-CHUN CHEN, CHIH-HUI HOU, WEI-CHU CHEN, YEN-HUI LU, TING-CHEN PAN, YEN-WEI LIN, BOR-CHEN TSAI
  • Patent number: 9500674
    Abstract: A probe structure includes a sleeve, a needle shaft and an elastic member. The needle shaft is accommodated in the sleeve and includes a first groove for accommodating the elastic member. The probe structure further includes a conductive component installed at the bottom of the sleeve and having an end connected into the first groove, and a second groove, so that the elastic member is situated in the first and second grooves. When the needle shaft is pressed and moved, the inner wall of the second groove is contacted with an outer sidewall of the conductive component to define a second conductive channel. With the two conductive channels, the effects of maintaining stable current transmission efficiency, reducing poor contact or disconnection, and providing good structural stability are achieved.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 22, 2016
    Assignee: C.C.P. CONTACT PROBES CO., LTD.
    Inventors: Yu-Min Cheng, You-Yu Lo, Chien-Yu Hsieh
  • Publication number: 20160223585
    Abstract: A probe structure includes a sleeve, a needle shaft and an elastic member. The needle shaft is accommodated in the sleeve and includes a first groove for accommodating the elastic member. The probe structure further includes a conductive component installed at the bottom of the sleeve and having an end connected into the first groove, and a second groove, so that the elastic member is situated in the first and second grooves. When the needle shaft is pressed and moved, the inner wall of the second groove is contacted with an outer sidewall of the conductive component to define a second conductive channel. With the two conductive channels, the effects of maintaining stable current transmission efficiency, reducing poor contact or disconnection, and providing good structural stability are achieved.
    Type: Application
    Filed: February 4, 2015
    Publication date: August 4, 2016
    Inventors: YU-MIN CHENG, YOU-YU LO, CHIEN-YU HSIEH
  • Patent number: 8717807
    Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: May 6, 2014
    Assignee: National Chiao Tung University
    Inventors: Ching-Te Chuang, Yin-Nien Chen, Chien-Yu Hsieh, Ming-Long Fan, Pi-Ho Hu, Pin Su
  • Publication number: 20130100731
    Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.
    Type: Application
    Filed: March 13, 2012
    Publication date: April 25, 2013
    Inventors: Ching-Te CHUANG, Yin-Nien Chen, Chien-Yu Hsieh, Ming-Long Fan, Pi-Ho Hu, Pin Su
  • Patent number: 8169814
    Abstract: The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: May 1, 2012
    Assignee: National Chiao Tung University
    Inventors: Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, Pi-Ho Hu, Pin Su
  • Publication number: 20120014171
    Abstract: The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.
    Type: Application
    Filed: September 7, 2010
    Publication date: January 19, 2012
    Inventors: Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, Pi-Ho Hu, Pin Su
  • Patent number: D787502
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: May 23, 2017
    Assignee: Acer Incorporated
    Inventors: Chien-Yu Hsieh, Hsueh-Chih Peng, Chun-Chieh Chiu, Ju-Hsien Weng, Tzu-Hsiang Chang, Te-Ho Chen, Hsing-Yi Kao, Wei-Yi Li
  • Patent number: D788768
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: June 6, 2017
    Assignee: Acer Incorporated
    Inventors: Chien-Yu Hsieh, Hsueh-Chih Peng, Chun-Chieh Chiu, Ju-Hsien Weng, Tzu-Hsiang Chang, Te-Ho Chen, Hsing-Yi Kao, Wei-Yi Li
  • Patent number: D873834
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 28, 2020
    Assignee: ACER INCORPORATED
    Inventors: Ju-Hsien Weng, Tzu-Hsiang Chang, Te-Ho Chen, Hsing-Yi Kao, Chien-Yu Hsieh, Wei-Yi Li, Yi-Ming Chang, Lun-Yu Hung, Cheng-Yu Cheng