Patents by Inventor Chien Yu Lai

Chien Yu Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250132851
    Abstract: A time synchronization method used for a time synchronization device is provided. The time synchronization device runs a plurality of Precision Time Protocol (PTP) instances to connect to a plurality of time synchronization domains through a plurality of ports. The time synchronization method includes selecting a grandmaster (GM) clock from the plurality of time synchronization domains; updating clock information of the grandmaster clock; determining whether each of the plurality of ports is a time receiving port or a time transmitting port according to the grandmaster clock; modifying clock attributes of each of the plurality of PTP instances according to whether the corresponding port is the time receiving port or the time transmitting port; and synchronizing, by the plurality of PTP instances, timings of the plurality of time synchronization domains according to the grandmaster clock.
    Type: Application
    Filed: February 1, 2024
    Publication date: April 24, 2025
    Applicant: Moxa Inc
    Inventors: Yi-Feng Lu, Chien-Yu Lai, Chi-Chuan Liu, Po-Hung Lin, Hou-Chen Liu
  • Publication number: 20250132852
    Abstract: A time synchronization method is provided for a time synchronization device, wherein the time synchronization device runs a plurality of precision time protocol (PTP) instances to connect to a plurality of time synchronization domains respectively. The time synchronization method includes determining whether a frequency of a local PTP clock of the time synchronization device is changed; and updating a frequency of a local clock of the time synchronization device with the frequency of the local PTP clock in response to the frequency of the local PTP clock being changed.
    Type: Application
    Filed: November 20, 2023
    Publication date: April 24, 2025
    Applicant: Moxa Inc.
    Inventors: Yi-Feng Lu, Chien-yu Lai, Chi-Chuan Liu, Po-Hung Lin, Hou-Chen Liu
  • Publication number: 20240204898
    Abstract: A time synchronization method for a plurality of time synchronization domains includes building a plurality of precision time protocol (PTP) instances corresponding to the plurality of time synchronization domains; determining a grandmaster clock; and synchronizing, by the plurality of PTP instances, timings of the plurality of time synchronization domains according to the grandmaster clock.
    Type: Application
    Filed: July 26, 2023
    Publication date: June 20, 2024
    Applicant: Moxa Inc.
    Inventors: Chi-Chuan Liu, Chun-Yu Lin, Chien-Yu Lai, Po-Hung Lin
  • Publication number: 20230421280
    Abstract: A time synchronization method for a time synchronization device, wherein the device is connected to a plurality of time synchronization domains through a plurality of ports, and the plurality of time synchronization domains use a plurality of PTP profiles. The method comprises determining whether each of the plurality of ports is a time receiving port or a time transmitting port; obtaining information of a grandmaster clock of the plurality of time synchronization domains; performing information conversion on the information of the grandmaster clock according to a PTP profile corresponding to each time transmitting port of the plurality of ports in the plurality of PTP profiles, so as to generate a plurality of clock information corresponding to each time transmitting port; and transmitting a corresponding clock information of the plurality of clock information to a corresponding time synchronization domain from each time transmitting port, so as to perform time synchronization.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 28, 2023
    Applicant: Moxa Inc.
    Inventors: Chi-Chuan Liu, Chun-Yu Lin, Chien-Yu Lai, Po-Hung Lin
  • Patent number: 11133959
    Abstract: An apparatus including a storage medium and a controller is provided. The storage medium stores a mapping of stream Identifiers (IDs) to Virtual Local Area Network (VLAN) tags. The controller is coupled to the storage medium and configured to route a packet for a Time-Sensitive Networking (TSN) network according to the mapping. The routing of the packet includes replacing a VLAN tag in the packet according to the stream ID of the packet and the mapping, so as to maintain the real-time deterministic behavior of delivering data streams in the TSN network.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 28, 2021
    Assignee: MOXA INC.
    Inventors: Chi-Chuan Liu, Chun-Yu Lin, Chien-Yu Lai, Wen-Lu Liao
  • Patent number: 11121889
    Abstract: An apparatus including a storage medium and a controller is provided. The storage medium stores a first mapping of stream Identifiers (IDs) to VLAN tags, and a second mapping of the stream IDs to VLAN tag indications. The controller is coupled to the storage medium and configured to route a packet between a Time-Sensitive Networking (TSN) network and a non-TSN network according to the first and second mappings. The routing of the packet includes inserting or removing a VLAN tag in or from the packet according to the stream ID of the packet and the first and second mappings, so as to enable interoperability between the TSN network and the non-TSN network.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 14, 2021
    Assignee: MOXA INC.
    Inventors: Chi-Chuan Liu, Chun-Yu Lin, Chien-Yu Lai, Wen-Lu Liao
  • Patent number: 10340822
    Abstract: A motor control system includes an electric motor and inverter. The electric motor includes a stator, rotor, and winding structure. The stator includes an iron core with a plurality of slots formed therein along a radial direction of the stator. The winding structure has a plurality of hairpin wires with pins disposed in the slots. The winding structure is configured to provide a plurality of phase windings and each phase winding includes a plurality of motor windings. The inverter includes a switching controller configured to control the turning-on and turning-off of the motor windings of each phase winding of the winding structure. When the electric motor operates in a high-speed mode, the switching controller controls the turning-on and turning-off of the motor windings of each phase winding such that a number of the phase windings turned-on is ? less than a number of all the phase windings.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 2, 2019
    Assignee: Delta Electronics, Inc.
    Inventors: Hong-Cheng Sheu, Chien-Yu Lai, I-Wen Tsai
  • Publication number: 20180375448
    Abstract: A motor control system includes an electric motor and inverter. The electric motor includes a stator, rotor, and winding structure. The stator includes an iron core with a plurality of slots formed therein along a radial direction of the stator. The winding structure has a plurality of hairpin wires with pins disposed in the slots. The winding structure is configured to provide a plurality of phase windings and each phase winding includes a plurality of motor windings. The inverter includes a switching controller configured to control the turning-on and turning-off of the motor windings of each phase winding of the winding structure. When the electric motor operates in a high-speed mode, the switching controller controls the turning-on and turning-off of the motor windings of each phase winding such that a number of the phase windings turned-on is 1/3 less than a number of all the phase windings.
    Type: Application
    Filed: April 24, 2018
    Publication date: December 27, 2018
    Inventors: Hong-Cheng SHEU, Chien-Yu LAI, I-Wen TSAI
  • Publication number: 20170289014
    Abstract: The present invention relates to a redundancy system of routing paths and method thereof. By establishing corresponding routing paths from different ports of routers in a ring network to a terminal in advance and transmitting the identical packet to the terminal by the different ports in the different routing paths simultaneously, the time of reestablishing the routing paths may be saved when one of the routing paths is broken, so as to improve the routing efficiency.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Kuo-Wei HSU, Chih-Chiang LAI, Shih-Chia YEN, Wen-Che HSU, Chien-Yu LAI
  • Publication number: 20170230231
    Abstract: In one embodiment of the invention, a redundancy system/method based on the Virtual Router Redundancy Protocol, it includes a master router and at least one backup router preselected. The master router and at least one backup router may have a weight value and Virtual LANs composed of same routing path. A communication representative is chosen from one of the Virtual LANs of each of the master router and the backup router. The communication representative of the master router may continuously transmit the advertisement packet to that of the backup router, and continuously transmit an Address Resolution Protocol table to the backup router. When a communication representative of the backup router doesn't receive the advertisement packet, all the Virtual LANs of the master router will be judged abnormal, and the master router may be replaced, therefore enhance the redundancy switching efficiency and increase the number of the available Virtual LANs.
    Type: Application
    Filed: February 7, 2016
    Publication date: August 10, 2017
    Inventors: Kuo-Wei HSU, Chih-Chiang LAI, Shih-Chia YEN, Wen-Che HSU, Chien-Yu LAI
  • Patent number: 6307904
    Abstract: An edge detector (10) detects edges of clock pulses in a digital signal and provides edge detect pulses to a state corrector (20). A state sequencer (15) receives a clock signal and steps through a sequence of states in accordance with the clock signal to generate a recovered clock signal which is substantially synchronized with the clock pulses in the digital signal. The state corrector (20) selectively providing reset states to reset the state sequencer in accordance with various parameters to maintain synchronization between the clock pulses in the digital signal and the recovered clock signal. The state corrector (20) also inhibits resetting the state sequencer (15) when edge detect pulse produced from instability in the edge detector (10) are received.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: October 23, 2001
    Assignee: Motorola. Inc.
    Inventors: Shih Sheng Hu, Chien Yu Lai
  • Patent number: D811359
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 27, 2018
    Assignee: DATALOGIC IP TECH S.R.L.
    Inventors: Thomas Burke, Joseph G. Mistkawi, Alessandro Chiarini, Marco D'Ulisse, Chien-Yu Lai, Huan-Pei Chen