Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.

Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: A time synchronization method for a time synchronization device, wherein the device is connected to a plurality of time synchronization domains through a plurality of ports, and the plurality of time synchronization domains use a plurality of PTP profiles. The method comprises determining whether each of the plurality of ports is a time receiving port or a time transmitting port; obtaining information of a grandmaster clock of the plurality of time synchronization domains; performing information conversion on the information of the grandmaster clock according to a PTP profile corresponding to each time transmitting port of the plurality of ports in the plurality of PTP profiles, so as to generate a plurality of clock information corresponding to each time transmitting port; and transmitting a corresponding clock information of the plurality of clock information to a corresponding time synchronization domain from each time transmitting port, so as to perform time synchronization.

Abstract: An apparatus including a storage medium and a controller is provided. The storage medium stores a mapping of stream Identifiers (IDs) to Virtual Local Area Network (VLAN) tags. The controller is coupled to the storage medium and configured to route a packet for a Time-Sensitive Networking (TSN) network according to the mapping. The routing of the packet includes replacing a VLAN tag in the packet according to the stream ID of the packet and the mapping, so as to maintain the real-time deterministic behavior of delivering data streams in the TSN network.

Abstract: An apparatus including a storage medium and a controller is provided. The storage medium stores a first mapping of stream Identifiers (IDs) to VLAN tags, and a second mapping of the stream IDs to VLAN tag indications. The controller is coupled to the storage medium and configured to route a packet between a Time-Sensitive Networking (TSN) network and a non-TSN network according to the first and second mappings. The routing of the packet includes inserting or removing a VLAN tag in or from the packet according to the stream ID of the packet and the first and second mappings, so as to enable interoperability between the TSN network and the non-TSN network.

Abstract: A motor control system includes an electric motor and inverter. The electric motor includes a stator, rotor, and winding structure. The stator includes an iron core with a plurality of slots formed therein along a radial direction of the stator. The winding structure has a plurality of hairpin wires with pins disposed in the slots. The winding structure is configured to provide a plurality of phase windings and each phase winding includes a plurality of motor windings. The inverter includes a switching controller configured to control the turning-on and turning-off of the motor windings of each phase winding of the winding structure. When the electric motor operates in a high-speed mode, the switching controller controls the turning-on and turning-off of the motor windings of each phase winding such that a number of the phase windings turned-on is ? less than a number of all the phase windings.

Abstract: A motor control system includes an electric motor and inverter. The electric motor includes a stator, rotor, and winding structure. The stator includes an iron core with a plurality of slots formed therein along a radial direction of the stator. The winding structure has a plurality of hairpin wires with pins disposed in the slots. The winding structure is configured to provide a plurality of phase windings and each phase winding includes a plurality of motor windings. The inverter includes a switching controller configured to control the turning-on and turning-off of the motor windings of each phase winding of the winding structure. When the electric motor operates in a high-speed mode, the switching controller controls the turning-on and turning-off of the motor windings of each phase winding such that a number of the phase windings turned-on is 1/3 less than a number of all the phase windings.

Abstract: The present invention relates to a redundancy system of routing paths and method thereof. By establishing corresponding routing paths from different ports of routers in a ring network to a terminal in advance and transmitting the identical packet to the terminal by the different ports in the different routing paths simultaneously, the time of reestablishing the routing paths may be saved when one of the routing paths is broken, so as to improve the routing efficiency.

Abstract: In one embodiment of the invention, a redundancy system/method based on the Virtual Router Redundancy Protocol, it includes a master router and at least one backup router preselected. The master router and at least one backup router may have a weight value and Virtual LANs composed of same routing path. A communication representative is chosen from one of the Virtual LANs of each of the master router and the backup router. The communication representative of the master router may continuously transmit the advertisement packet to that of the backup router, and continuously transmit an Address Resolution Protocol table to the backup router. When a communication representative of the backup router doesn't receive the advertisement packet, all the Virtual LANs of the master router will be judged abnormal, and the master router may be replaced, therefore enhance the redundancy switching efficiency and increase the number of the available Virtual LANs.

Abstract: An edge detector (10) detects edges of clock pulses in a digital signal and provides edge detect pulses to a state corrector (20). A state sequencer (15) receives a clock signal and steps through a sequence of states in accordance with the clock signal to generate a recovered clock signal which is substantially synchronized with the clock pulses in the digital signal. The state corrector (20) selectively providing reset states to reset the state sequencer in accordance with various parameters to maintain synchronization between the clock pulses in the digital signal and the recovered clock signal. The state corrector (20) also inhibits resetting the state sequencer (15) when edge detect pulse produced from instability in the edge detector (10) are received.