Abstract: A system for increasing the extraction of an active ingredient includes a vacuum quick-dissolving tank, a mixer, a solid-liquid separator, and a homogenizer. The vacuum quick-dissolving tank receives a sample. The mixer is connected to the vacuum quick-dissolving tank, and provides an aqueous solvent to be mixed with the sample. Heating, cooling, stirring, and vacuuming in the vacuum quick-dissolving tank make the sample dissolve and emulsify repeatedly between the vacuum quick-dissolving tank and the mixer to produce a mixture, which is output by the vacuum quick-dissolving tank. The solid-liquid separator receives the mixture output from the vacuum quick-dissolving tank for solid-liquid separation, and outputs an isolated sample liquid. The homogenizer receives the sample liquid output from the solid-liquid separator, performs high-pressure homogenization to obtain an extract liquid containing an active ingredient, and outputs the extract liquid.

Abstract: A system for increasing the extraction of an active ingredient includes a vacuum quick-dissolving tank, a mixer, a solid-liquid separator, and a homogenizer. The vacuum quick-dissolving tank receives a sample. The mixer is connected to the vacuum quick-dissolving tank, and provides an aqueous solvent to be mixed with the sample. Heating, cooling, stirring, and vacuuming in the vacuum quick-dissolving tank make the sample dissolve and emulsify repeatedly between the vacuum quick-dissolving tank and the mixer to produce a mixture, which is output by the vacuum quick-dissolving tank. The solid-liquid separator receives the mixture output from the vacuum quick-dissolving tank for solid-liquid separation, and outputs an isolated sample liquid. The homogenizer receives the sample liquid output from the solid-liquid separator, performs high-pressure homogenization to obtain an extract liquid containing an active ingredient, and outputs the extract liquid.

Abstract: A method for extracting active ingredient(s) from a raw material to be extracted is provided. The method comprises the following steps: (1) mixing a raw material to be extracted with an aqueous solvent to provide a mixture; (2) conducting a homogenization to the mixture to obtain a first extract with active ingredient(s); and (3) conducting a high pressure homogenization to the first extract to obtain a second extract with active ingredient(s), wherein the homogenization in step (2) is conducted at a temperature ranging from normal temperature to 100° C.

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract: A failure alarm system adapted for monitoring an instrument includes a BUS transmitting data and control logics inside the failure alarm system, a recording device connected to the BUS for recording operating sounds of the instrument, a voice processing unit connected to the BUS for converting the operating sounds into a voice eigenvector, a storage unit connected to the BUS for storing the voice eigenvector at the normal working state of the instrument as historical data and also storing the voice eigenvector at the abnormal working state of the instrument therein, a comparing unit connected to the BUS for comparing the new voice eigenvector with the previous voice eigenvector saved as the historical data to judge whether the instrument is at the abnormal working state, and a warning unit connected to the BUS for warning the monitoring personnel when the abnormal state is detected.

Abstract: A failure alarm system adapted for monitoring an instrument includes a BUS transmitting data and control logics inside the failure alarm system, a recording device connected to the BUS for recording operating sounds of the instrument, a voice processing unit connected to the BUS for converting the operating sounds into voice eigenvector, a storage unit connected to the BUS for storing the voice eigenvector at the normal working state of the instrument as historical data and also storing the voice eigenvector at the abnormal working state of the instrument therein, a comparing unit connected to the BUS for comparing new voice eigenvector with the pervious voice eigenvector saved as the historical data to judge whether the instrument is at abnormal working state, and a warning unit connected to the BUS for warning the monitoring personnel when abnormal state is detected.

Abstract: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.

Abstract: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract: A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.