Patents by Inventor Chien-Yuan Chen

Chien-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12230632
    Abstract: An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Yuan Chen, Hau-Tai Shieh
  • Publication number: 20240412774
    Abstract: The present disclosure provides a memory device, including a memory array, a tracking circuit, a memory controller, and a word line driver. A plurality of word lines are in communication with a plurality of memory cells of the memory array. The memory controller decodes a memory address of a memory access command to generate a decoded row address signal. The word line driver is configured to assert one of the plurality of word lines in response to the decoded row address signal. In response to detecting a switching event of a clock control signal derived from an input clock signal of the memory device, the memory controller asserts an tracking acceleration signal obtained from a tracking word line of the memory device to activate one or more first tracking arrays of the plurality of tracking arrays to pull down a voltage level of a tracking bit line.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 12, 2024
    Inventors: CHIEN-YUAN CHEN, HAU-TAI SHIEH, CHENG HUNG LEE
  • Publication number: 20240386949
    Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Che-An Lee, Hau-Tai Shieh, Cheng Hung Lee
  • Publication number: 20240387670
    Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Kuo-Feng Yu, Jiao-Hao Chen, Chih-Yu Hsu, Chih-Wei Lee, Chien-Yuan Chen
  • Publication number: 20240379444
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Patent number: 12142657
    Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Feng Yu, Jiao-Hao Chen, Chih-Yu Hsu, Chih-Wei Lee, Chien-Yuan Chen
  • Patent number: 12080604
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Publication number: 20240266228
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240198180
    Abstract: A training course recommendation device and a training course recommendation method are provided. The training course recommendation device includes a course database, a rider database, and a course recommendation processing module. The course database is configured to store a plurality of riding training courses. The rider database is configured to store rider characteristic data and riding sensing data. The course recommendation processing module is configured to analyze the rider characteristic data and the riding sensing data to obtain a user riding characteristic vector, compare the user riding characteristic vector and a course characteristic vector of each of the plurality of riding training courses to obtain a plurality of matching values of the plurality of riding training courses, and set at least one recommendation course from the plurality of riding training courses according to the matching value(s) which is(are) greater than a threshold.
    Type: Application
    Filed: March 25, 2023
    Publication date: June 20, 2024
    Inventors: Chien-Yuan CHEN, Chun-Cheng CHEN, Shao-Hong YANG, Jen-Sheng TSAI
  • Publication number: 20240198179
    Abstract: A cycling sport training suggestion system (10) includes a sport real-time analysis module (102), a cyclist information module (104), a route feature module (106) and a sport role data base (108). The cyclist information module (104) transmits a cyclist real-time sense information (110) to the sport real-time analysis module (102). The route feature module (106) transmits a route feature information (112) to the sport real-time analysis module (102). The sport role data base (108) transmits a cyclist historical sport information (114) and a perfect cyclist sport information (116) to the sport real-time analysis module (102). The sport real-time analysis module (102) integrates and analyzes the cyclist real-time sense information (110), the route feature information (112), the cyclist historical sport information (114) and the perfect cyclist sport information (116) to generate a cycling sport training suggestion signal (118).
    Type: Application
    Filed: March 25, 2023
    Publication date: June 20, 2024
    Inventors: Chien-Yuan CHEN, Chun-Cheng CHEN, Shao-Hong YANG, Jen-Sheng TSAI
  • Publication number: 20240192576
    Abstract: A camera module suited for assembled in a casing is provided. The camera module includes a camera and a switch cover. The camera is disposed in the casing and aligned with a camera hole of the casing. The switch cover is slidably disposed in the casing, wherein the switch cover includes a sliding member and a shielding member secured to the sliding member, and a thickness of the shielding member is less than a thickness of the sliding member. The camera hole is seated on a sliding path of the shielding member. The shielding member is suited for blocking between the camera and the camera hole or moving out between the camera and the camera hole. An electronic device is also provided.
    Type: Application
    Filed: August 13, 2023
    Publication date: June 13, 2024
    Applicant: Acer Incorporated
    Inventors: Yu-Chin Huang, Cheng-Mao Chang, Li-Hua Hu, Pao-Min Huang, Chien-Yuan Chen
  • Patent number: 11990378
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240096400
    Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.
    Type: Application
    Filed: January 23, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan CHEN, Hau-Tai SHIEH, Cheng Hung LEE
  • Patent number: 11854970
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Publication number: 20230411216
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 21, 2023
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Publication number: 20230398406
    Abstract: A cycling sport performance level analysis system includes an artificial intelligence classification analysis module, a bicycle apparatus, a classification knowledge rule module and a cyclist information module. The classification knowledge rule module transmits a classification test task rule including a track information to the artificial intelligence classification analysis module and the bicycle apparatus. The bicycle apparatus performs the classification test task rule and collects a sport sensing information which is sensed to transmit the sport sensing information to the artificial intelligence classification analysis module. The cyclist information module transmits a cyclist basic information and a track historical riding information to the artificial intelligence classification analysis module.
    Type: Application
    Filed: March 25, 2023
    Publication date: December 14, 2023
    Inventors: Chien-Yuan CHEN, Chun-Cheng CHEN, Shao-Hong YANG, Jen-Sheng TSAI
  • Publication number: 20230395432
    Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.
    Type: Application
    Filed: June 4, 2022
    Publication date: December 7, 2023
    Inventors: Chien-Yuan Chen, Kuo-Feng Yu, Jian-Hao Chen, Chih-Yu Hsu, Yao-Teng Chuang, Shan-Mei Liao
  • Publication number: 20230386567
    Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao
  • Publication number: 20230378063
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Publication number: 20230369110
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and an S/D contact structure formed adjacent to the gate structure. The FinFET device structure includes a protection layer formed on the S/D contact structure, and an S/D conductive plug formed over the protection layer. The S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan CHEN, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG