Abstract: A memory card and a control chip capable of supporting various voltage supplies and a method of supporting voltages are discussed. The memory card includes a flash memory and a control chip for controlling the flash memory, and the control chip has a voltage regulator, a pad power supplier, a core controller and an output circuit. The voltage regulator transforms an external working voltage into a working voltage. The pad power supplier receives the external working voltage and adjusts a level of the external working voltage to output a pad working voltage according to an operating mode. The core controller receives the working voltage to work and generates a control signal. The output circuit receives the control signal and outputs a memory control signal according to a level of the pad working voltage. The control chip controls a flash memory with the memory control signal.

Abstract: A memory card and a control chip capable of supporting various voltage supplies and a method of supporting voltages thereof are provided. The memory card comprises a flash memory and a control chip for controlling the flash memory, and the control chip has a voltage regulator, a pad power supplier, a core controller and an output circuit. The voltage regulator transforms an external working voltage into a working voltage. The pad power supplier receives the external working voltage and adjusts a level of the external working voltage to output a pad working voltage according to an operating mode. The core controller receives the working voltage to work and generates a control signal. The output circuit receives the control signal and outputs a memory control signal according to a level of the pad working voltage. The control chip controls a flash memory with the memory control signal.

Abstract: A circuit and a method for measuring the read operation delay on DRAM bit lines are disclosed. The circuit comprises a plurality of circuit blocks connected in series, each having a 1-bit DRAM cell. The output of the DRAM cell in each circuit block is connected to the word line of the DRAM cell of the next circuit block through inverters, so the read operation in the DRAM cell of the next circuit block is triggered. The total delay between the word line at the first circuit block and the output of the last circuit block can be measured on the oscilloscope. The delay for every 1-bit DRAM cell is equal to the total delay divided by the number of circuit blocks.