Abstract: At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.

Abstract: At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.

Abstract: At least one processor may receive components of a vector, wherein each of the components of the vector comprises at least an exponent. The at least one processor may further determine a maximum exponent out of respective exponents of the components of the vector, and may determine a scaling value based at least in part on the maximum exponent. An arithmetic logic unit of the at least one processor may scale the vector, by subtracting the scaling value from each of the respective exponents of the components of the vector.

Abstract: A method and apparatus for reordering the vertices of a graphics primitive. The vertices of the primitive are received in a circular order, but the position of the vertices in the circular order is arbitrary. The vertices include coordinates with respect to an origin. Comparison logic operates on the coordinates of each vertex to determine which vertex is the minimum vertex, which the vertex that is a minimum distance away from the origin. Once the minimum vertex is known, the vertices are shuffled into the proper order, with the minimum vertex in the lowest order position, the next vertex in circular order in the next position and so on. An apparatus saves the information for reordering the vertices, so that the order is preserved for parameter information for each vertex.

Abstract: A method and apparatus for reordering the vertices of a graphics primitive. The vertices of the primitive are received in a circular order, but the position of the vertices in the circular order is arbitrary. The vertices include coordinates with respect to an origin. Comparison logic operates on the coordinates of each vertex to determine which vertex is the minimum vertex, which the vertex that is a minimum distance away from the origin. Once the minimum vertex is known, the vertices are shuffled into the proper order, with the minimum vertex in the lowest order position, the next vertex in circular order in the next position and so on. An apparatus saves the information for reordering the vertices, so that the order is preserved for parameter information for each vertex.