Patents by Inventor Chien-Ting Lin
Chien-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12727344Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.Type: GrantFiled: April 18, 2023Date of Patent: September 1, 2026Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Yi-Feng Hsu
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Publication number: 20260255667Abstract: A semiconductor device includes a substrate, a first transistor, a second transistor and a third transistor. The substrate includes a high-voltage (HV) area, a medium-voltage (MV) area, and a low-voltage (LV) area. The first transistor is disposed in the HV area and includes a first gate dielectric layer and a first gate electrode. The second transistor is disposed in the LV area and includes a plurality of fin-shaped structures and a second gate electrode. The third transistor is disposed in the MV area and includes a third gate dielectric layer and a third gate electrode. The topmost surfaces of the first gate electrode, the second gate electrode and the third gate electrode are coplanar with each other.Type: ApplicationFiled: April 20, 2026Publication date: August 27, 2026Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin
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Publication number: 20260239787Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.Type: ApplicationFiled: February 13, 2026Publication date: August 13, 2026Applicant: United Microelectronics Corp.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chun-Ting Yeh
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Patent number: 12687194Abstract: A triaxial spherical universal joint structure includes: a body; a sphere; and a rotating shaft, wherein the body is provided with a sphere accommodating part and a rotating shaft accommodating part adjacent to each other in up-and-down directions, the sphere accommodating part extends upward to form an opening of the sphere accommodating part, the rotating shaft accommodating part extends downward to form an opening of the rotating shaft accommodating part, the body is provided with a notch extending from the opening of the sphere accommodating part to the opening of the rotating shaft accommodating part, the sphere accommodating part and the rotating shaft accommodating part are communicated with the external space via the notch, a fixing assembly is provided on the body at a position close to the notch and the opening of the sphere accommodating part, the rotating shaft may rotate horizontally in the rotating shaft accommodating part.Type: GrantFiled: July 20, 2022Date of Patent: July 21, 2026Inventor: Chien-Ting Lin
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Patent number: 12677473Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.Type: GrantFiled: July 11, 2023Date of Patent: July 7, 2026Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Chien-Ting Lin, Ssu-I Fu, Chin-Hung Chen
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Publication number: 20260181996Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having through-silicon vias (TSVs) therein, forming an inorganic layer on the substrate, forming an organic layer on the inorganic layer, and then bonding dies having different functionalities on the organic layer. Preferably, the dies include a radio-frequency integrated circuit (RFIC) die, a power amplifier (PA) die, and/or a high electron mobility transistor (HEMT) die.Type: ApplicationFiled: February 9, 2025Publication date: June 25, 2026Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chu-Fu Lin, Chuan-Lan Lin, Min-Shiang Hsu, Chien-Ting Lin, Yu-Ping Wang
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Publication number: 20260150167Abstract: An LED driver and an operating method thereof are provided. The LED driver includes a conversion circuit, a switch circuit and a control circuit. The positive and negative output terminals of the conversion circuit are electrically coupled to the LED light source through two switches of the switch circuit respectively. After the control circuit receives a light-off command, the control circuit generates the dimming signal to configure the conversion circuit to decrease the output current; and when the control circuit determines that the output current is less than a turn-off current threshold, the control circuit configures the two switches of the switch circuit to be in a non-conduction state.Type: ApplicationFiled: July 15, 2025Publication date: May 28, 2026Inventors: Ching-Ho Chou, Yung-Chuan Lu, Ming-Lung Hsieh, Chien-Ting Lin
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Patent number: 12635231Abstract: A semiconductor device includes a substrate, a first transistor, a second transistor and a third transistor. The substrate includes a high-voltage (HV) area, a medium-voltage (MV) area, and a low-voltage (LV) area. The first transistor is disposed in the HV area and includes a first gate dielectric layer and a first gate electrode. The second transistor is disposed in the LV area and includes a plurality of fin-shaped structures and a second gate electrode. The third transistor is disposed in the MV area and includes a third gate dielectric layer and a third gate electrode. The topmost surfaces of the first gate electrode, the second gate electrode and the third gate electrode are coplanar with each other.Type: GrantFiled: February 10, 2022Date of Patent: May 19, 2026Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin
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Publication number: 20260136443Abstract: An LED driver and an operating method thereof are provided. The LED driver includes conversion circuits and a control circuit. The conversion circuits are configured to be electrically coupled to LED light sources for supplying power. The control circuit is configured to: configure the conversion circuits to generate output currents and output voltages; calculate output powers of the conversion circuits; sum up the output powers of the conversion circuits to obtain a total output power; and when it is determined that the total output power is greater than a power limit, configure at least one of the conversion circuits to reduce at least one of the output currents according to the power limit and according to at least one of the total output power and the output powers of the conversion circuits, so as to reduce the total output power to be less than or equal to the power limit.Type: ApplicationFiled: June 24, 2025Publication date: May 14, 2026Inventors: Ching-Ho Chou, Yung-Chuan Lu, Ming-Lung Hsieh, Chien-Ting Lin
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Publication number: 20260132881Abstract: Provided is a quick-assembly adapter, wherein a screw fastener is accommodated within a central accommodating portion of a base, a rotating ring is sleeved around fixing portions of the base, each of gear accommodating portions of the base accommodates two horizontally adjacent second gears, second teeth of the two adjacent second gears are meshed with each other, the second teeth close to the central accommodating portion are meshed with first teeth of a first gear of the screw fastener, the second teeth close to the rotating ring are meshed with inner teeth of the rotating ring, and fasteners fix a carrying member with the base. When rotating the rotating ring, the inner teeth drive the second teeth, making the two adjacent second gears rotate in opposite directions, and the second teeth drive the first teeth, such that the screw fastener rotates in a direction same as the rotating ring.Type: ApplicationFiled: November 7, 2025Publication date: May 14, 2026Inventor: Chien-Ting Lin
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Publication number: 20260130177Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric ((IMD) layer on the substrate and a first metal interconnection in the first IMD layer, forming a bonding pad on the first IMD layer, forming a passivation layer on the bonding pad, removing part of the passivation layer to expose the bonding pad, performing a chip probing test on the bonding pad, removing the bonding pad to form a recess, forming a dielectric layer to fill the recess completely, and forming a second metal interconnection in the dielectric layer.Type: ApplicationFiled: December 8, 2024Publication date: May 7, 2026Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Ting Lin, Chuan-Lan Lin, Chu-Fu Lin
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Publication number: 20260107846Abstract: A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.Type: ApplicationFiled: December 16, 2025Publication date: April 16, 2026Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Chien-Ting Lin, Yu-Hsiang Lin, Ssu-I Fu, Chih-Kai Hsu
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Patent number: 12588338Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.Type: GrantFiled: December 9, 2022Date of Patent: March 24, 2026Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chun-Ting Yeh
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Publication number: 20260047485Abstract: A method for fabricating semiconductor device includes the steps of first providing a first wafer and a second wafer, performing a first dicing process to separate the first wafer into first dies, bonding the first dies onto the second wafer, forming a first molding layer around the first dies, forming first bumps on the first dies, performing a second dicing process to separate the second wafer for forming second dies, and then bonding the first dies onto a third wafer.Type: ApplicationFiled: September 23, 2024Publication date: February 12, 2026Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Chu-Fu Lin, Min-Shiang Hsu, Chien-Ting Lin
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Patent number: 12543250Abstract: An LED driver, an LED lighting system and an operating method thereof are provided. The LED driver is for driving an LED light source and includes a strobe circuit and a DC-DC converter. The strobe circuit generates a low-frequency modulation signal. The DC-DC converter is coupled to the strobe circuit and is configured to provide an adjustable operating current to the LED light source according to a DC signal and the low-frequency modulation signal. The operating current includes a DC current signal and a low-frequency AC current signal corresponding to the DC signal and the low-frequency modulation signal respectively. A frequency of the low-frequency AC current signal is between 25 Hz and 100 Hz, and a current ripple factor, equaling a difference of a maximum value and a minimum value of the operating current divided by a sum of the maximum value and the minimum value, is less than 8%.Type: GrantFiled: June 12, 2024Date of Patent: February 3, 2026Assignee: Delta Electronics, Inc.Inventors: Ching-Ho Chou, Yung-Chuan Lu, Tsung-Ta Wu, Chien-Ting Lin
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Publication number: 20260018466Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.Type: ApplicationFiled: September 22, 2025Publication date: January 15, 2026Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo
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Patent number: 12525596Abstract: A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.Type: GrantFiled: February 16, 2022Date of Patent: January 13, 2026Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Chien-Ting Lin, Yu-Hsiang Lin, Ssu-I Fu, Chih-Kai Hsu
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Publication number: 20260013402Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a spacer adjacent to the MTJ and the first SOT layer, and a second SOT layer on the first SOT layer. Preferably, the first SOT layer and the second SOT layer are made of same material.Type: ApplicationFiled: September 11, 2025Publication date: January 8, 2026Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
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Patent number: 12514866Abstract: Provided herein are methods for treating or ameliorating malignant diseases, such as cancers. Also provided herein are methods of increasing the immunity of an immune cell toward malignant cells.Type: GrantFiled: January 19, 2022Date of Patent: January 6, 2026Assignee: National Taiwan UniversityInventors: Hsing-Chen Tsai, Chien-Ting Lin, Chong-Jen Yu, Tai-Chung Huang, Rueyhung Roc Weng, Hsuan-Hsuan Lu, Jung-Chi Liao
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Patent number: D1118305Type: GrantFiled: May 27, 2024Date of Patent: March 17, 2026Inventor: Chien-Ting Lin