Patents by Inventor Chieri Teramoto

Chieri Teramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including barrier metal and coating film and method for manufacturing same
    Publication number: 20080290523
    Abstract: A semiconductor device includes an interconnection layer provided on a substrate, a first insulating film provided on the substrate, and on the interconnection layer so as to coat the interconnection layer, the first insulating film includes a silicon oxide film, a second insulating film provided on the first insulating film, the second insulating film includes either a silicon oxynitride film or a silicon nitride film, and an insulative coating film provided on the second insulating film.
    Type: Application
    Filed: April 23, 2008
    Publication date: November 27, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Chieri Teramoto
  • Alignment pattern for a semiconductor device manufacturing process
    Publication number: 20050233580
    Abstract: An alignment pattern comprises at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over the surface of the substrate and a flat surface of a metal plug, and the flat surface being lower in level than the top surface of the inter-layer insulator. The metal plug is buried within an alignment hole which completely penetrates the insulation layer and at least reaches the field oxide film, so that the alignment hole has a bottom level which is deeper than a bottom level of the inter-layer insulator.
    Type: Application
    Filed: June 15, 2005
    Publication date: October 20, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Chieri Teramoto
  • Alignment pattern for a semiconductor device manufacturing process
    Patent number: 6917115
    Abstract: An alignment pattern comprises at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over the surface of the substrate and a flat surface of a metal plug, and the flat surface being lower in level than the top surface of the inter-layer insulator. The metal plug is buried within an alignment hole which completely penetrates the insulation layer and at least reaches the field oxide film, so that the alignment hole has a bottom level which is deeper than a bottom level of the inter-layer insulator.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: July 12, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Chieri Teramoto
  • Alignment pattern and method of forming the same
    Publication number: 20030102576
    Abstract: An alignment pattern comprises at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over the surface of the substrate and a flat surface of a metal plug, and the flat surface being lower in level than the top surface of the inter-layer insulator. The metal plug is buried within an alignment hole which completely penetrates the insulation layer and at least reaches the field oxide film, so that the alignment hole has a bottom level which is deeper than a bottom level of the inter-layer insulator.
    Type: Application
    Filed: December 2, 2002
    Publication date: June 5, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Chieri Teramoto