Patents by Inventor Chiew Khiang Kuit

Chiew Khiang Kuit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240402245
    Abstract: An integrated circuit includes an output circuit. The output circuit includes first, second, and third external contacts, a first output buffer circuit coupled to the first external contact, a first resistive circuit coupled between the first external contact and the second external contact, a second output buffer circuit coupled to the third external contact, and a second resistive circuit coupled between the second external contact and the third external contact. The output circuit has a test mode of operation to test for leakage current on the first and the third external contacts in response to receiving a first voltage applied externally to the first and the second resistive circuits through the second external contact. The output circuit has a user mode of operation wherein a supply voltage is applied externally to the first and the second resistive circuits through the second external contact.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 5, 2024
    Applicant: Altera Corporation
    Inventors: Chiew Khiang Kuit, Ching Sia Lim, Ann Poh Gan
  • Patent number: 9874607
    Abstract: The present invention discloses a method of testing an analog-to-digital converter (ADC). The method includes receiving a series of analog signals from a tester site, converting the series of analog signals to a series of digital code words using an ADC, evaluating the ADC based on the series of digital code words using an ADC test setup and generating an output signal identifying whether the ADC has passed the testing.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 23, 2018
    Assignee: Altera Corporation
    Inventors: Chiew Khiang Kuit, Chee Lam Ng, Tze Sin Tan, Nen Wei Ng
  • Patent number: 8327199
    Abstract: Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: December 4, 2012
    Assignee: Altera Corporation
    Inventors: Jayabrata Ghosh Dastidar, Chiew Khiang Kuit, Siew Ling Yeoh, Jun Pin Tan, Kok Sun Chia, Yee Liang Tan, Kar Keng Chua