Patents by Inventor Chiew Nyuk Ho

Chiew Nyuk Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200013880
    Abstract: An integrated circuit device that includes a substrate as a base of the integrated circuit device, a semiconductor layer disposed on top of the substrate, an isolation layer disposed on top of the semiconductor layer, a plurality of metals disposed above the isolation layer, a transistor including a source and drain region positioned in the semiconductor layer, and a gate electrode connected to the source and drain region and positioned in the isolation layer, wherein the source and drain region, and gate electrode are respectively connected to the metals by electrical contacts, and a Faraday shield positioned laterally between the gate electrode and the drain region in the isolation layer. The Faraday shield is connected to one of the metals through at least one conductive interconnect produced by a damascene process such that the interconnect forms a continuous connection to the metal from the Faraday shield.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 9, 2020
    Inventors: Chiew Nyuk Ho, Arjun Kumar Kantimahanti, Venkatesh A/L Madhaven, Seok Man Yun, Saw Li Lee, Thart Liang Ong