Patents by Inventor Chiew Sin Ping

Chiew Sin Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7259071
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 21, 2007
    Assignee: SilTerra Malaysia Sdn.Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 7241665
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: July 10, 2007
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
  • Patent number: 6818514
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: November 16, 2004
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Publication number: 20040166698
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Application
    Filed: February 26, 2003
    Publication date: August 26, 2004
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 6362045
    Abstract: A new method of forming non-volatile memory cells with an improved bottom silicon dioxide layer of the O—N—O has been achieved. A semiconductor substrate is provided. A tunneling dielectric layer is grown overlying the semiconductor substrate. A polysilicon layer is deposited overlying the tunneling dielectric layer. Nitrogen is implanted into the polysilicon layer to form a nitridized surface region. The polysilicon layer and the tunneling dielectric layer are then patterned to form floating gates. A bottom silicon dioxide layer is grown overlying the floating gates by thermal oxidation of the polysilicon layer. The nitridized surface region reduces the rate of thermal oxidation and creates a smooth surface. A silicon nitride layer is deposited overlying the bottom silicon dioxide layer. A top silicon dioxide layer is formed overlying the silicon nitride layer to complete the O—N—O stack.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: March 26, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yung-Tao Lin, Chwa Siow Lee, Chiew Sin Ping