Patents by Inventor Chih-An Lin

Chih-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376093
    Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 2, 2021
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210375724
    Abstract: A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang SHAO, Wen-Lin SHIH, Su-Chun YANG, Chih-Hang TUNG, Chen-Hua YU
  • Publication number: 20210376054
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation layer covering the magnetic element and a portion of the semiconductor substrate. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding edges of the magnetic element.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chun-Yi WU, Kuang-Yi WU, Hon-Lin HUANG, Chih-Hung SU, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20210375946
    Abstract: A radio frequency integrated circuit includes a silicon CMOS substrate with at least one CMOS device buried therein, and at least one thin film transistor formed on the silicon CMOS substrate and functioning as a radio frequency device. The thin film transistor includes a T-shaped gate electrode. A method for the fabricating a radio frequency integrated circuit is also disclosed.
    Type: Application
    Filed: July 27, 2020
    Publication date: December 2, 2021
    Inventors: Horng-Chih Lin, Yu-An Huang
  • Publication number: 20210375858
    Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.
    Type: Application
    Filed: March 12, 2021
    Publication date: December 2, 2021
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
  • Publication number: 20210369852
    Abstract: Disclosed herein is a method for preparing a hyaluronan-drug conjugate. The method uses the ethyl cyano(hydroxyimino)acetate/diisopropylcarbodiimide coupling system in a homogeneous reaction phase, which unexpectedly improves the substitution rate and substitution efficiency of hyaluronan-drug conjugates for various drugs.
    Type: Application
    Filed: December 10, 2020
    Publication date: December 2, 2021
    Applicant: Aihol Corporation
    Inventors: Szu-Yuan LEE, Ping-Shan LAI, Chih-An LIN
  • Publication number: 20210375885
    Abstract: A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Publication number: 20210375760
    Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Hsiang-Lun Kao, Hsiang-Wei Liu, Tai-I Yang, Jian-Hua Chen, Yu-Chieh Liao, Yung-Chih Wang, Tien-Lu Lin
  • Publication number: 20210375766
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Publication number: 20210374577
    Abstract: One or more computing devices, systems, and/or methods for cross-domain action prediction are provided. Action sequence embeddings are generated based upon a textual embedding and a graph embedding utilizing past user action sequences corresponding to sequences of past actions performed by users across a plurality of domains. An autoencoder is trained to utilize the action sequence embeddings to project the action sequence embeddings to obtain intent space vectors. A service switch classifier is trained using the intent space vectors. In response to the service switch classifier predicting that a current user will switch from a current domain to a next domain, the current user is provided with a recommendation of an action corresponding to the next domain.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Su-Chen Lin, Zhungxun Liao, Jian-Chih Ou, Tzu-Chiang Liou
  • Patent number: 11189913
    Abstract: An antenna structure serving as a radar emitter with extended long range function comprises a radiating element comprised of radiating units connected in series by a feeder. Each two adjacent radiating units are spaced apart from each other by a specified distance. Lengths of the radiating units are same, and width of the radiating units gradually decreases from a center to ends. The feeder transmits a current signal to the radiating element. The radiating element emits a radar beam based on the current signal.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 30, 2021
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Kuo-Cheng Chen, Yi-Ming Chen, Siang-Yu Siao, Zheng Lin, Teng-Bang Hou, Chih-Chung Hsieh
  • Patent number: 11189687
    Abstract: A semiconductor device includes and an active region and a peripheral region. The peripheral region includes a seal region. The semiconductor device includes a substrate and a seed layer one the substrate. The semiconductor device also includes a GaN-containing composite layer on the seed layer, and the GaN-containing composite layer is disposed in the active region and the peripheral region. The semiconductor device also includes a gate electrode, a source electrode and a drain electrode disposed on the GaN-containing composite layer within the active region. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. The semiconductor device further includes a sealing structure, and the sealing structure includes a barrier structure and a seal component in the seal region. The barrier structure is disposed around the active region. The barrier structure penetrates the GaN-containing composite layer and the seed layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 30, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Chieh Chou, Hsin-Chih Lin
  • Patent number: 11188224
    Abstract: A controlling method of a user interface and an electronic device are provided. A touch element includes a start area, a trigger area and a track area connecting the start area and the trigger area. The controlling method of the user interface includes following steps: entering a startup interface display mode according to the touch behavior performed on the touch element; generating continuous touch data in response to the touch behavior when the touch behavior moves from the start area to the track area and an animation trigger condition is satisfied, activating an animation mode according to the continuous touch data; and generating the continuous touch data in response to the touch behavior when the touch behavior moves from the start area to the track area and from the track area to the trigger area, and opening a user interface according to the continuous touch data.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 30, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Ya-Ting Chen, Chien-Chih Tseng, Wei-Tong Lin, Chao-Chieh Cheng
  • Patent number: 11189658
    Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Hsien Wei, Chung-Te Lin, Han-Ting Tsai, Tai-Yen Peng, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Wei-Chih Wen
  • Publication number: 20210366084
    Abstract: Aspects of the present disclosure relate to QCFA deblurring. An example method includes obtaining an image to be processed and determining an average of pixel values between a first one or more pixels and a second one or more pixels of the image. The second one or more pixels neighbor the first one or more pixels. The method also includes determining a difference between pixel values of the first one or more pixels and the second one or more pixels, generating one or more weights based on the average and the difference, and combining the average and the difference based on the one or more weights to generate a deblurred pixel value. A processed image includes one or more deblurred pixel values.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventors: Yang-Yao Lin, Shang-Chih Chuang, Chung-Chi Tsai, Xiaoyun Jiang
  • Publication number: 20210366783
    Abstract: A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.
    Type: Application
    Filed: May 20, 2020
    Publication date: November 25, 2021
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20210366726
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20210366816
    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE
  • Publication number: 20210366529
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
  • Patent number: D936822
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 23, 2021
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Pei-Chuan Lee, Yi-Chih Lin, Chu-Hsien Chou