Patents by Inventor Chih-An Lin

Chih-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11158989
    Abstract: A device includes a laser source, an amplifier, an optical sensor and a spectrometer. The laser source is configured to produce a seed laser beam. The amplifier includes gain medium and a discharging unit. The discharging unit is configured to pump the gain medium for amplifying power of the seed laser beam. The optical sensor is coupled to the amplifier and configured for sensing an optical emission generated in the amplifier while the gain medium is discharging. The spectrometer is coupled with the optical sensor and configured to measure a spectrum of the optical emission.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Henry Yee-Shian Tong, Wen-Chih Wang, Hsin-Liang Chen, Louis Chun-Lin Chang, Cheng-Chieh Chen, Li-Jui Chen, Po-Chung Cheng, Jeng-Yann Tsay
  • Patent number: 11158742
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 11157029
    Abstract: A voltage regulator includes an error amplification circuit, a voltage detection circuit, a loop current prevention circuit, a voltage regulation circuit, and a stable voltage output terminal; the voltage regulation circuit outputs a voltage of the second power supply to the stable voltage output terminal when receiving a first control signal and second control signal output by the voltage detection circuit and stops outputting the voltage of the second power supply when receiving a third control signal and fourth control signal output by the voltage detection circuit; the loop current prevention circuit prevents a loop from being formed between the first power supply and the stable voltage output terminal when receiving the first control signal and the second control signal and controls the error amplification circuit to output an error amplification signal to the stable voltage output terminal when receiving the third control signal and the fourth control signal.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: October 26, 2021
    Assignee: SEEYA OPTRONICS CO., LTD.
    Inventors: Ping-lin Liu, Chih-pu Yeh
  • Publication number: 20210329664
    Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Chiao-Chih Chang, Chien-Liang Lin, Jen-Hao Hsueh, Cheng-Che Chen, Sheng-Yi Ho, I-Wei Tsai, Zhen Jiang, Wen-Jean Yang
  • Publication number: 20210327866
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Application
    Filed: July 21, 2020
    Publication date: October 21, 2021
    Inventors: Chen-Hua Yu, Yung-Chi Lin, Wen-Chih Chiou
  • Publication number: 20210327836
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20210328034
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 21, 2021
    Inventors: Yu-Chu LIN, Chia-Ming PAN, Chi-Chung JEN, Wen-Chih CHIANG, Keng-Ying LIAO, Huai-jen TUNG
  • Patent number: 11152477
    Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20210316413
    Abstract: A method for detecting and compensating CNC tools being implemented in an electronic device, receives from a detector first parameters and second parameters in respect of a first tool. Such first parameters include at least one of service life, blade break information, and blade chipping information of the first tool, and such second parameters include at least one of length extension information, length wear information, radial wear information, and blade thickness wear information of the first tool. Based on the first parameters, instructions to process the workpiece are transmitted or not. Upon receiving the second parameters, instructions to adjust operation of the first tool are transmitted, to compensate for deterioration in normal use.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 14, 2021
    Inventors: HSING-CHIH HSU, ZHAO-YAO YI, LEI ZHU, CHANG-LI ZHANG, ER-YANG MA, CHIH-SHENG LIN, FENG XIE, MING-TAO LUO
  • Publication number: 20210320097
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20210318982
    Abstract: Disclosed is a data transfer system capable of accelerating data transmission between two chips. The data transfer system includes: a master system-on-a-chip (SoC) including a master transmission circular buffer and a master reception circular buffer; and a slave SoC including a slave reception circular buffer and a slave transmission circular buffer. The slave/master reception circular buffer is a duplicate of the master/slave transmission circular buffer; accordingly, the write pointers of the two corresponding buffers are substantially synchronous and the read pointers of the two corresponding buffers are substantially synchronous as well. In light of the above, the read and write operations of the master/slave transmission circular buffer can be treated as the read and write operations of the slave/master reception circular buffer; therefore some conventional data reproducing procedure(s) for the data transmission can be omitted and the data transmission is accelerated.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 14, 2021
    Inventors: PO-LIN WEI, PI-MING LEE, CHIH-CHIANG YANG
  • Publication number: 20210320052
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Wei-Tao Tsai
  • Patent number: 11145718
    Abstract: The disclosure provides a semiconductor device having a separate active region and a method of fabricating the same. The semiconductor device includes a substrate, a plurality of isolation islands, a source region, and a drain region. The substrate includes a first active region, a second active region, and a plurality of separate active regions. The separate active regions are connected to the first active region and the second active region. The separate active regions and the isolation islands are alternately disposed. The gate structure includes a body portion and a plurality of extensions. The body portion disposed on a portion of the first active region. The extensions are coupled to the body portion and extend from the body portion to the isolation islands. The source region and the drain region are respectively located in the substrate in the first active region and the second active region.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: October 12, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Wei-Chih Lin
  • Patent number: 11145713
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Patent number: 11145760
    Abstract: A semiconductor structure includes an active semiconductor fin having a first height, a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height, an isolation structure between the active semiconductor fin and the dummy semiconductor fin, and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 12, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Kuan Jung Chen, I-Chih Chen, Chih-Mu Huang, Ching-Pin Lin, Sheng-Lin Hsieh
  • Patent number: 11143906
    Abstract: A reflective LCD panel includes a color filter substrate, an array substrate, a liquid crystal layer and a polarizing film. The array substrate and the color filter substrate are disposed oppositely. The liquid crystal layer is disposed between the color filter substrate and the array substrate and has an alignment direction. The polarizing film is disposed on the color filter substrate, and color coordinates of the polarizing film in the CIE1976 color space are (a, b), wherein 0.05?a?0.2 and ?5?b?0. The liquid crystal layer has a birefringence difference ?n, the liquid crystal layer has a thickness (d), when the reflective LCD panel is in a white frame, 2?n*d=?? is satisfied, ?? is the optical path difference obtained when a forward light vertically enters the liquid crystal layer and is reflected by the array substrate, and 120 nm??n*d?170 nm.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 12, 2021
    Assignee: HANNSTAR DISPLAY CORPORATION
    Inventors: Ding-Wei Liu, Meng-Ju Li, Wei-Chih Hsu, Chen-Hao Su, Sung-Chun Lin, Chia-Hua Yu
  • Patent number: 11145623
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Patent number: 11145734
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; a gate structure wrapping each of the semiconductor layers; a spacer structure wrapping an edge portion of each of the semiconductor layers; and a dummy fin structure contacting a sidewall of the gate structure, wherein the dummy fin structure is separated from a sidewall of the spacer structure by a dielectric liner.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11145789
    Abstract: A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 12, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Che-Hung Lin, Chien-Chih Liao, Chi-Shiang Hsu, De-Shan Kuo, Chao-Hsing Chen
  • Publication number: 20210313388
    Abstract: A light-emitting device comprises a substrate; a first light-emitting unit and a second light-emitting unit formed on the substrate, each of the first light-emitting unit and the second light-emitting unit comprises a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first light-emitting unit comprises a first semiconductor mesa and a first surrounding part surrounding the first semiconductor mesa, and the second light-emitting unit comprises a second semiconductor mesa and a second surrounding part surrounding the second semiconductor mesa; a trench formed between the first light-emitting unit and the second light-emitting unit and exposing the substrate; a first insulating layer comprising a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and a connecting electrode comprising a first connecting part on the first
    Type: Application
    Filed: June 15, 2021
    Publication date: October 7, 2021
    Inventors: Chao-Hsing CHEN, I-Lun MA, Bo-Jiun HU, Yu-Ling LIN, Chien-Chih LIAO