Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: Provided are a package structure having a joint structure and a method of forming the same. The package structure includes: a first under bump metallurgy (UBM) structure disposed on a first dielectric layer, wherein the first UBM structure at least comprises: a barrier layer embedded in the first dielectric layer; and an upper metal layer disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer, and a portion of a top surface of the barrier layer is exposed by the first dielectric layer; and a solder layer disposed on the first UBM structure and contacting the upper metal layer.

Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.

Abstract: A multi-pixel detector of an image sensor is described. The multi-pixel detector includes a first photodiode region disposed within a semiconductor substrate to form a first pixel, a second photodiode region disposed within the semiconductor substrate to form a second pixel adjacent to the first pixel, and a partial isolation structure extending from a first side of the semiconductor substrate towards a second side of the semiconductor substrate between the first photodiode region and the second photodiode region. A length of a lateral portion of the partial isolation structure between the first photodiode region and the second photodiode region is less than a lateral length of the first photodiode region.

Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.

Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: An ear canal clamp for small animals includes a base and a clamping mechanism. The clamping mechanism includes two clamping arms movably mounted on the base, a biasing member mounted on the base and constrained between the clamping arms, and two ear canal positioning members mounted respectively to the clamping arms and facing each other. The clamping arms are configured to move toward each other and compress the biasing member to increase the distance between the ear canal positioning members. A biasing force generated by the biasing member when compressed is used to push the clamping arms to move oppositely with respect to each other.

Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Abstract: A manufacturing method of a waveguide and a head mounted display device having the waveguide are provided. The head mounted display device includes a display unit, a first waveguide and a second waveguide. The display unit is configured to provide an image beam. The first waveguide is located between the display unit and the second waveguide. The first waveguide is configured to transmit the image beam to the second waveguide and adjust a light shape of the image beam to maintain a field angle and expand a pupil in a single dimension. The second waveguide is configured to transmit the image beam to outside of the head mounted display device, and the second waveguide can extend a light transmission path and provide a uniform image beam.

Abstract: A power dividing and combining device comprising a resonance body, a plurality of circuit boards, an upper cover and a lower cover is provided. The resonance body comprises a solid conductive body, a plurality of first dividing elements, a plurality of second dividing elements, a signal-receiving end and a signal-transmitting end. The solid conductive body has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connecting the first surface and the second surface. The first dividing elements are disposed on the first surface and separate a plurality of first resonance channels on the first surface. The first resonance channels intersect at a first common region on the first surface. The second dividing elements are disposed on the second surface and separate a plurality of second resonance channels on the second surface. The second resonance channels intersect at a second common region on the second surface.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: A data retransmission method includes configuring the quantity of code block groups in a transport block and configuring a plurality of physical resource groups; configuring the quantity of physical resources included in each of the physical resource groups according to the different quantities of code block groups; selecting the physical resources included in the physical resource group that corresponds to the initial transmission to send the transport block; determining the quantity of code block groups that were erroneously sent in the transport block according to the response; selecting one of the physical resources in one of the physical resource groups that corresponds to the retransmission to send at least one code block group that was erroneously sent according to the quantity of code block groups that were erroneously sent; and completing the retransmission only after all of the code block groups in the transport block have been successfully sent.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.