Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A semiconductor package includes a substrate, a semiconductor die mounted on the substrate, and a heatsink over the semiconductor die. The heatsink includes a roof portion and at least one connecting portion extending between the roof portion and the substrate. The at least one connecting portion includes a connection lead mounted on a connection pad of the substrate. The connection pad includes a first portion and a second portion spaced apart from each other, which are configured to electrically couple to different voltage signals, respectively, for detecting heatsink floating.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A semiconductor package includes a substrate, a semiconductor die mounted on the substrate, and a heatsink over the semiconductor die. The heatsink includes a roof portion and at least one connecting portion extending between the roof portion and the substrate. The at least one connecting portion includes a connection lead mounted on a connection pad of the substrate. The connection pad includes a first portion and a second portion spaced apart from each other, which are configured to electrically couple to different voltage signals, respectively, for detecting heatsink floating.

Abstract: A chip packaging structure includes a chip, a passive component, and at least two metal lines. In the chip, first bonding pads, second bonding pads and connecting pads are disposed above an integrated circuit, and the second bonding pads and the connecting pads are separated from the integrated circuit. The second bonding pads are electrically connected to the corresponding connecting pads, respectively. The passive component is disposed on the chip, and includes two electrodes that are respectively electrically connected to and adhered to one of the corresponding connecting pad. The metal lines are disposed on the chip, and have one end thereof respectively connected to the second bonding pads, and the other end respectively connected to the first bonding pads.

Abstract: A controlling method for recording digital television programs is disclosed herein. The controlling method includes steps as follows. A service information packet is received from a digital television system terminal. The service information packet is valid within a time limitation and the service information packet includes an event information table corresponding to a plurality of program episodes. When one of the program episodes is assigned to be a first recording target and a predetermined recording period exceeds the time limitation, the service information packet is demodulated to obtain an event information section of the first recording target from the event information table. When the service information packet is updated, a matching procedure is performed on the event information section of the first recording target with the updated service information packet. A matched program episode is added into a scheduled recording target list automatically.

Abstract: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the substrate and the second pads are located on a second surface of the substrate. The first interconnecting structure is coupled with the chip, one of the first pads and one of the second pads for flexible design of various applications. A substrate of the chip package is also disclosed.

Abstract: An IC package method capable of decreasing IR drop of a chip and associated IC apparatus is provided. The IC package method comprises forming a lead frame including a die paddle and a plurality of fingers; installing a die on the die paddle, and coupling a plurality of signal terminals of the die to the fingers; forming a power transferring unit coupled to a power supply; coupling power reception terminals of a plurality of logic units in the die to the power transferring unit; and forming a housing for encapsulating the die, the lead frame and the power transferring unit.

Abstract: A chip package and fabricating method thereof are provided to maintain the thermal dissipating efficiency and reduce the damage to the chip. The edge of the exposed portion would be cracked caused by external force because of the substrate of the chip is brittle. The crack in the edge of the chip will degrade the reliability and induce the malfunction of the chip. In this case, the chip is disposed at least one elastic element at the edges of the exposed side to reduce the risk of the crack in the chip.

Abstract: An electronic apparatus includes a package, a circuit board, a thermal dissipating module and a thermal transmitting module. The package includes a substrate, a heat source and a plurality of electric terminals electrically connected to the circuit board. The heat source and the electric terminals are disposed on a surface of the substrate facing to the circuit board. The heat source is located between the substrate and the circuit board. The thermal transmitting module passes through the electric connection structures between the package and the circuit board and connects the heat source of the package with the thermal dissipating module. Thus, the thermal transmitting module enhances the thermal dissipating efficiency for the heat source of the package and improves the reliability of the electronic apparatus.

Abstract: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the substrate and the second pads are located on a second surface of the substrate. The first interconnecting structure is coupled with the chip, one of the first pads and one of the second pads for flexible design of various applications. A substrate of the chip package is also disclosed.

Abstract: An electronic apparatus includes a package, a circuit board, a thermal dissipating module and a thermal transmitting module. The package includes a substrate, a heat source and a plurality of electric terminals electrically connected to the circuit board. The heat source and the electric terminals are disposed on a surface of the substrate facing to the circuit board. The heat source is located between the substrate and the circuit board. The thermal transmitting module passes through the electric connection structures between the package and the circuit board and connects the heat source of the package with the thermal dissipating module. Thus, the thermal transmitting module enhances the thermal dissipating efficiency for the heat source of the package and improves the reliability of the electronic apparatus.

Abstract: A contact structure on a chip is disclosed. The contact is disposed on a metallic pad of the chip. The contact structure includes a bump and a buffer layer. The bump is disposed on the metallic pad. The buffer layer is disposed on the chip to surround the interface between the bump and the metallic pad. A weakest inter-metallic compound naturally formed between the metallic pad and the bump will be protected by the buffer layer and far away from the stress concentration point for increasing the reliability of a flip chip package.

Abstract: The present invention provides a circuit carrier for connecting to at least a bump. The circuit carrier comprises a substrate, at least a contact pad on a surface of the substrate and a solder mask layer covering the substrate. The solder mask has at least a stepped opening that exposes a portion of the contact pad. The stepped opening includes at least a first opening and a second opening and the size of the first opening is larger than that of the second opening. The stepped opening of the solder mask layer can contain more pre-solder paste, thus increasing the bonding strength between the bump and the contact pad.

Abstract: A chip package and fabricating method thereof are provided to maintain the thermal dissipating efficiency and reduce the damage to the chip. The edge of the exposed portion would be cracked caused by external force because of the substrate of the chip is brittle. The crack in the edge of the chip will degrade the reliability and induce the malfunction of the chip. In this case, the chip is disposed at least one elastic element at the edges of the exposed side to reduce the risk of the crack in the chip.