Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.

Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.

Abstract: A signal processing system includes a first transceiver unit, a second transceiver unit, a protocol analysis circuit, a system chip, and a network unit. The first transceiver unit can transceive a first optical signal and a first electrical signal. The second transceiver unit can transceive a second optical signal and a second electrical signal. The protocol analysis circuit can process the first electrical signal and an analysis signal related to the first optical signal. The system chip can process the analysis signal, the second electrical signal, a first operation signal and a second operation signal. The network unit can transceive the first operation signal and the second operation signal, and transceive a first network signal and a second network signal between the network unit and a user device. The system chip and the network unit can process signals related to the first optical signal and the second optical signal.

Abstract: The present invention discloses a microwave heating system for desorbing contaminated soil, comprising: a feeding module; a heating cavity; a first microwave suppression cavity; a second microwave suppression cavity; a conveyor belt; a feeding device; and an exhaust module. The feeding device is arranged above the first microwave suppression cavity or the second microwave suppression cavity, and the feeding device contains a microwave absorber material. The invention further discloses a microwave heating process for desorption of polluted soil. With the microwave heating system and process for desorbing contaminated soil, the contaminated soil can be heated quickly and uniformly, and quickly cooled and taken out smoothly.

Abstract: Compounds, compositions and methods are provided for modulating the activity of EP2 and EP4 receptors, and for the treatment, prevention and amelioration of one or more symptoms of diseases or disorders related to the activity of EP2 and EP4 receptors. In certain embodiments, the compounds are antagonists of both the EP2 and EP4 receptors.

Abstract: The disclosure provides a data privacy protection method, a server device, and a client device for federated learning. A public dataset is used to perform model training on a machine learning model by a server device to generate a gradient pool including multiple first gradients. The gradient pool and the machine learning model are received by a client device. The client device uses a local dataset to perform model training on the machine learning model to obtain a second gradient. A local gradient is selected from the first gradients in the gradient pool according to the second gradient using a differential privacy algorithm by the client device. An aggregated machine learning model is generated by performing model aggregation based on the local gradient by the server device.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

Abstract: A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a first movable assembly and a first driving assembly. The first movable assembly is configured to connect a first optical element, and the first movable assembly is movable relative to the fixed assembly. The first driving assembly is configured to drive the first movable assembly to move relative to the fixed assembly in a first dimension.

Abstract: An electronic device includes a substrate, a side wiring, a protective film, and a first filler. The substrate has a first surface, a second surface, and a side surface connected between the first surface and the second surface. The side wiring is disposed on the substrate and extends from the first surface to the second surface through the side surface. The protective film is disposed on the side wiring. The side wiring is sandwiched between the substrate and the protective film. An edge of the protective film extends beyond a side wall of the side wiring, and the protective film, the side wall of the side wiring, and the substrate define a gap. The first filler is disposed on the protective film and in the gap, wherein the first filler includes a first material and a plurality of particles mixed within the first material.

Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.

Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.