Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.

Abstract: A temperature sensing circuit that includes a bandgap voltage generation circuit, a current mirror branch, a variable resistor, a comparator circuit, a control circuit and a temperature determining circuit. The bandgap voltage generation circuit generates a bandgap voltage. The current mirror branch generates a mirrored current mirrored from the bandgap voltage generation circuit. The variable resistor is electrically coupled to the current mirror branch to receive the mirrored current to generate a variable voltage. The comparator circuit compares the bandgap voltage and the variable voltage to generate a comparison result. The control circuit generates a control signal according to the comparison result to adjust the resistance of the variable resistor and outputs a signal value when the signal value forces the variable voltage to be equal to the bandgap voltage. The temperature determining circuit generates a temperature value according to the signal value.

Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.

Abstract: A frame assembly includes a carrier and a frame. The carrier includes a bottom wall, and inner and outer side walls. The bottom wall is formed with an opening. The inner side wall is located in the opening. The inner and outer side walls extend from the bottom wall along an upright direction. The inner and outer side walls respectively include first inner and outer engaging structures. The outer side wall is spaced from the inner side wall. The frame includes a frame body, and inner and outer lateral walls. The inner and outer lateral walls extend from the frame body and respectively include second inner and outer engaging structures. The outer lateral wall is spaced from the inner lateral wall. The first and second inner engaging structures are engaged with each other, and the first and second outer engaging structures are engaged with each other.

Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.

Abstract: A frame assembly includes a carrier and a frame. The carrier includes a bottom wall, and inner and outer side walls. The bottom wall is formed with an opening. The inner side wall is located in the opening. The inner and outer side walls extend from the bottom wall along an upright direction. The inner and outer side walls respectively include first inner and outer engaging structures. The outer side wall is spaced from the inner side wall. The frame includes a frame body, and inner and outer lateral walls. The inner and outer lateral walls extend from the frame body and respectively include second inner and outer engaging structures. The outer lateral wall is spaced from the inner lateral wall. The first and second inner engaging structures are engaged with each other, and the first and second outer engaging structures are engaged with each other.

Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.