Abstract: An image monitoring system includes a first control interface, a second control interface, a recording module, a storage device, and a control circuit. The recording module generates an image monitoring data. The storage device stores the image monitoring data. The control circuit is controlled by the first control interface and the second control interface. The control circuit performs a system operation in respect of the image monitoring data according to a first trigger signal when the first control interface receives the first trigger signal and performs the system operation in respect of the image monitoring data according to a second trigger signal when the second control interface receives the second trigger signal. The first control interface is different from the second control interface, and the first trigger signal is different from the second trigger signal.

Abstract: A mobile communication terminal system includes a serial interface port, a multimedia output/input module, a multimedia processor, a frequency-signal output/input module, and a baseband processor. The serial interface port is coupled to a computer system via a serial interface. The multimedia output/input module provides a first input signal. The multimedia processor processes the first input signal to generate a first serial interface signal. The frequency-signal output/input module provides a second input signal. The baseband processor processes the second input signal to generate a second serial interface signal to the multimedia processor.

Abstract: A mobile communication terminal system includes a serial interface port, a multimedia output/input module, a multimedia processor, a frequency-signal output/input module, and a baseband processor. The serial interface port is coupled to a computer system via a serial interface. The multimedia output/input module provides a first input signal. The multimedia processor processes the first input signal to generate a first serial interface signal. The frequency-signal output/input module provides a second input signal. The baseband processor processes the second input signal to generate a second serial interface signal to the multimedia processor.

Abstract: An apparatus for acquiring an image and a method therefor. The apparatus is electrically connected to an image sensor for acquiring an acquired image and outputting an original image signal. The apparatus includes an image processor, a data reduction unit and a buffer. The image processor generates a first image signal according to the original image signal. The data reduction unit reduces a data amount of the first image signal to generate a second image signal. The buffer stores the second image signal.

Abstract: An apparatus for acquiring an image and a method therefor. The apparatus is electrically connected to an image sensor for acquiring an acquired image and outputting an original image signal. The apparatus includes an image processor, a data reduction unit and a buffer. The image processor generates a first image signal according to the original image signal. The data reduction unit reduces a data amount of the first image signal to generate a second image signal. The buffer stores the second image signal.

Abstract: A computer architecture that incorporates display memory into system memory is disclosed, which comprises a memory, a memory controller and a display controller. Both of the memory controller and the display controller are employed to control access of the memory device having system data and display data stored therein. Built-in signals and an arbiter are provided between the controllers to arbitrate the priorities of the two controllers to access the memory device. Furthermore, request and grant signals are used to initiate the refresh of the main memory to maintain data therein. The control circuits of the two controllers to the memory device are connected to each other to prevent signals contention.

Abstract: An arbitration bus is arranged between a core logic chip set and a plurality of peripheral devices in order to arbitrate requests by the peripheral devices to use system memory of a computer system. Three or two arbitration signals carried on the arbitration bus. Means are provided to differentiate two levels of priority in each peripheral device. The core logic chip set can make a response pressing or otherwise so as to promote the overall performance. Preemption is provided so that peripheral devices can be overridden without wasting time when it is necessary to do so. Each peripheral device outputs a row address strobe (RAS) signal, all of which are connected together to form a open-collector signal to the core logic chip set for automatically accessing corresponding memory banks of system memory.