Patents by Inventor Chih-Chang Hung
Chih-Chang Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10867998Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: GrantFiled: January 2, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Publication number: 20200388616Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: ApplicationFiled: August 24, 2020Publication date: December 10, 2020Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 10854603Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: GrantFiled: May 29, 2019Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Patent number: 10833077Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: GrantFiled: May 9, 2019Date of Patent: November 10, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Patent number: 10756087Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: GrantFiled: June 15, 2018Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20200119153Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Mrunal A. KHADERBAD, Hsueh Wen TSAU, Chia-Ching LEE, Da-Yuan LEE, Hsiao-Kuan WEI, Chih-Chang HUNG, Huicheng CHANG, Weng CHANG
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Publication number: 20200105613Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.Type: ApplicationFiled: January 15, 2019Publication date: April 2, 2020Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20200066900Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: I-Wei YANG, Chih-Chang HUNG, Shu-Yuan KU, Ryan Chia-Jen CHEN, Ming-Ching CHANG
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Publication number: 20200052090Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first metal gate stack and a second metal gate stack over a semiconductor substrate. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack. The semiconductor device structure further includes an insulating structure between the first metal gate stack and the second metal gate stack. The insulating structure has a first convex surface facing towards the first metal gate stack.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsuan HSIAO, Shu-Yuan KU, Chih-Chang HUNG, I-Wei YANG, Chih-Ming SUN
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Publication number: 20200006334Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: May 29, 2019Publication date: January 2, 2020Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Publication number: 20190386002Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 10510854Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.Type: GrantFiled: June 29, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mrunal A. Khaderbad, Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung, Huicheng Chang, Weng Chang
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Patent number: 10468527Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.Type: GrantFiled: August 15, 2018Date of Patent: November 5, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Wei Yang, Chih-Chang Hung, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
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Patent number: 10461171Abstract: A method for forming a semiconductor device structure includes forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack. The method includes removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer and removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer. The method includes partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess. The method includes forming an insulating structure to partially or completely fill the recess.Type: GrantFiled: April 27, 2018Date of Patent: October 29, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsuan Hsiao, Shu-Yuan Ku, Chih-Chang Hung, I-Wei Yang, Chih-Ming Sun
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Publication number: 20190267374Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: ApplicationFiled: May 9, 2019Publication date: August 29, 2019Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Publication number: 20190221653Abstract: A method for forming a semiconductor device structure includes forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack. The method includes removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer and removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer. The method includes partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess. The method includes forming an insulating structure to partially or completely fill the recess.Type: ApplicationFiled: April 27, 2018Publication date: July 18, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsuan HSIAO, Shu-Yuan KU, Chih-Chang HUNG, I-Wei YANG, Chih-Ming SUN
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Publication number: 20190164837Abstract: A semiconductor structure with cutting depth control and method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, fins protruding from a substrate are formed. Next, source/drain devices are grown on both ends of the fins. Then, an inter-layer dielectric layer crossing the fins and enclosing the source/drain devices is deposited. A metal gate structure enclosed by the inter-layer dielectric layer is formed between the source/drain devices. And then, a replacement operation is performed to replace a portion of the inter-layer dielectric layer with an isolation material, thereby forming an isolation portion that adjoins the metal gate structure and is located between the adjacent source/drain devices. Thereafter, a metal gate cut operation is performed, thereby forming an opening in the metal gate structure and an opening in the isolation portion, and an insulating material is deposited in the openings.Type: ApplicationFiled: January 21, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chang HUNG, Shu-Yuan KU, I-Wei YANG, Yi-Hsuan HSIAO, Ming-Ching CHANG, Ryan Chia-Jen CHEN
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Publication number: 20190148539Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.Type: ApplicationFiled: August 15, 2018Publication date: May 16, 2019Inventors: I-Wei Yang, Chih-Chang Hung, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
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Publication number: 20180308944Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Inventors: Mrunal A. KHADERBAD, Hsueh Wen TSAU, Chia-Ching LEE, Da-Yuan LEE, Hsiao-Kuan WEI, Chih-Chang HUNG, Huicheng CHANG, Weng CHANG
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Patent number: 10014382Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.Type: GrantFiled: March 13, 2014Date of Patent: July 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mrunal A. Khaderbad, Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung, Huicheng Chang, Weng Chang