Patents by Inventor Chih-Chang Lee
Chih-Chang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942550Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.Type: GrantFiled: February 24, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
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Patent number: 11939664Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Chun Hsieh, Tsung-Yu Tsai, Hsing-Yuan Huang, Chih-Chang Wu, Szu-Hua Wu, Chin-Szu Lee
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Publication number: 20240094625Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Chih-Cheng LIN, Chia-Jen CHEN
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Patent number: 11929767Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.Type: GrantFiled: August 16, 2022Date of Patent: March 12, 2024Assignee: MEDIATEK INC.Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
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Patent number: 11916110Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.Type: GrantFiled: July 4, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ching Wang, Wei-Yang Lee, Ming-Chang Wen, Jo-Tzu Hung, Wen-Hsing Hsieh, Kuan-Lun Cheng
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Patent number: 11914286Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.Type: GrantFiled: April 4, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Amo Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, Jeng-Horng Chen
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Patent number: 8237499Abstract: The present disclosure illustrates a feedforward controlled envelope modulator and a feedforward control circuit thereof. The feedforward controlled envelope modulator comprises a linear amplifier circuit, a switching amplifier, and a feedforward control circuit. The linear amplifier circuit amplifies an input voltage signal, so as to output an output voltage signal to a load node. The switching amplifier receives a comparison signal, and outputs a switching current to the load node according to the comparison signal. The feedforward control circuit comprises a duplicate linear amplifier circuit and a hysteresis comparator. The duplicate linear amplifier circuit amplifies the input voltage signal, so as to output a reference voltage signal, wherein an amplifying gain of the duplicate linear amplifier circuit is identical to an amplifying gain of the linear amplifier circuit. The hysteresis comparator compares the output voltage signal and the reference voltage signal, so as to output the comparison signal.Type: GrantFiled: May 7, 2010Date of Patent: August 7, 2012Assignee: Industrial Technology Research InstituteInventors: Chun-Jen Chen, Chih-Chang Lee
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Publication number: 20110273235Abstract: The present disclosure illustrates a feedforward controlled envelope modulator and a feedforward control circuit thereof. The feedforward controlled envelope modulator comprises a linear amplifier circuit, a switching amplifier, and a feedforward control circuit. The linear amplifier circuit amplifies an input voltage signal, so as to output an output voltage signal to a load node. The switching amplifier receives a comparison signal, and outputs a switching current to the load node according to the comparison signal. The feedforward control circuit comprises a duplicate linear amplifier circuit and a hysteresis comparator. The duplicate linear amplifier circuit amplifies the input voltage signal, so as to output a reference voltage signal, wherein an amplifying gain of the duplicate linear amplifier circuit is identical to an amplifying gain of the linear amplifier circuit. The hysteresis comparator compares the output voltage signal and the reference voltage signal, so as to output the comparison signal.Type: ApplicationFiled: May 7, 2010Publication date: November 10, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chun-Jen Chen, Chih-Chang Lee
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Patent number: 7330366Abstract: A DC-AC converter is applicable for transforming direct current (DC) to alternating current (AC). The DC-AC converter includes a voltage boost module and a DC-AC converter module. Herein the voltage boost module includes a voltage bypass circuit and a voltage boost circuit, both of which receive input voltage from DC input power. Meantime, the voltage bypass circuit sends out the received input voltage, and the voltage boost circuit will operate to increase DC output voltage from the DC input as the DC output voltage from the voltage bypass circuit is not high enough to meet requirement by AC output power. The DC-AC converter module receives the output voltage from the voltage boost module and converts the received voltage to the required AC output power.Type: GrantFiled: June 7, 2005Date of Patent: February 12, 2008Assignee: DELTA Electronics, Inc.Inventors: Chih-Chang Lee, Lei-Ming Lee
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Publication number: 20060098461Abstract: A DC-AC converter is applicable for transforming direct current (DC) to alternating current (AC). The DC-AC converter includes a voltage boost module and a DC-AC converter module. Herein the voltage boost module includes a voltage bypass circuit and a voltage boost circuit, both of which receive input voltage from DC input power. Meantime, the voltage bypass circuit sends out the received input voltage, and the voltage boost circuit will operate to increase DC output voltage from the DC input as the DC output voltage from the voltage bypass circuit is not high enough to meet requirement by AC output power. The DC-AC converter module receives the output voltage from the voltage boost module and converts the received voltage to the required AC output power.Type: ApplicationFiled: June 7, 2005Publication date: May 11, 2006Inventors: Chih-Chang Lee, Lei-Ming Lee
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Publication number: 20050064293Abstract: A mixture of an electrolyte, a first oligomer and an initiating agent is emulsion polymerized to form a precursor solution with a micro void structure for the gel-type electrolyte. A current available jelly-roll is put into an aluminum foil packet, and the precursor solution is then injected into the packet, which is then sealed and baked so that a highly conductive gel-type electrolyte is disposed inside and outside the jelly-roll. The lithium battery with the gel-type electrolyte is very stiff, reliable, and free from expansion and electrolyte leakage.Type: ApplicationFiled: September 19, 2003Publication date: March 24, 2005Inventors: Chih-Hung Shen, Shun-Ming Huang, Chih-Ming Chen, Chih-Chang Lee
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Publication number: 20040149375Abstract: The present invention provides a method for encapsulating a secondary battery. The method first impregnates a fiber fabric with a resin composition, and then a first heating process is performed to form an adhesive sheet. A jelly-roll of a battery is encapsulated with the adhesive sheet, and then a second heating process is performed to cure the adhesive sheet completely. The first heating process initiates a preliminary reaction to transform the resin composition into a B state to form an adhesive sheet, and the adhesive sheet in the B state is convenient to be further processed or stored. Since the adhesive sheet in the B state possesses a property capable of further curing, the adhesive sheet can be processed into any shape when a further curing process is performed. Therefore, the battery can be easily manufactured with a curved, wound or any arbitrary shape, and the thickness of the battery will not be increased obviously.Type: ApplicationFiled: February 5, 2003Publication date: August 5, 2004Inventors: Shun-Ming Huang, Chih-Chang Lee, Mei-Hui Wang, Chih-Ming Chen