Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

Abstract: A method for synthesizing a lane image is proposed in the present application. This method includes the following steps. M continuous image frames are retrieved at a frame rate f from a video image capture device. A quantity N for image mapping is determined based on a dash length L of a dashed line and a distance S between two dashes of the dashed lines. A frame interval for mapping image frames is determined based on the dash length L, the distance S, the velocity v, and the frame rate f. At least N image frames are retrieved from the M continuous image frames at the frame interval. The at least N image frames are synthesized to obtain the lane image using an image synthesizing device.

Abstract: A method for synthesizing a lane image is proposed in the present application. This method includes the following steps. M continuous image frames are retrieved at a frame rate f from a video image capture device. A quantity N for image mapping is determined based on a dash length L of a dashed line and a distance S between two dashes of the dashed lines. A frame interval for mapping image frames is determined based on the dash length L, the distance S, the velocity v, and the frame rate f. At least N image frames are retrieved from the M continuous image frames at the frame interval. The at least N image frames are synthesized to obtain the lane image using an image synthesizing device.

Abstract: A pixel structure is provided. The pixel structure includes an active device, a first pixel electrode, a second pixel electrode, and a conductive line. The first pixel electrode is electrically connected to the active device. The second pixel electrode and the first pixel electrode are electrically insulated. The conductive line is located below the first pixel electrode and the second pixel electrode. The active device is electrically connected to the first pixel electrode through the conductive line. The conductive line is coupled to the second pixel electrode to form a coupling capacitance.

Abstract: A method for synthesizing a lane image is proposed in the present application. This method includes the following steps. M continuous image frames are retrieved at a frame rate f from a video image capture device. A quantity N for image mapping is determined based on a dash length L of a dashed line and a distance S between two dashes of the dashed lines. A frame interval for mapping image frames is determined based on the dash length L, the distance S, the velocity v, and the frame rate f. At least N image frames are retrieved from the M continuous image frames at the frame interval. The at least N image frames are synthesized to obtain the lane image using an image synthesizing device.

Abstract: A pixel structure is provided. The pixel structure includes an active device, a first pixel electrode, a second pixel electrode, and a conductive line. The first pixel electrode is electrically connected to the active device. The second pixel electrode and the first pixel electrode are electrically insulated. The conductive line is located below the first pixel electrode and the second pixel electrode. The active device is electrically connected to the first pixel electrode through the conductive line. The conductive line is coupled to the second pixel electrode to form a coupling capacitance.

Abstract: A pixel structure is provided. The pixel structure includes an active device, a first pixel electrode, a second pixel electrode, and a conductive line. The first pixel electrode is electrically connected to the active device. The second pixel electrode and the first pixel electrode are electrically insulated. The conductive line is located below the first pixel electrode and the second pixel electrode. The active device is electrically connected to the first pixel electrode through the conductive line. The conductive line is coupled to the second pixel electrode to form a coupling capacitance.

Abstract: A pixel structure is provided. The pixel structure includes a control device, a main pixel electrode, and a sub pixel electrode. The main pixel electrode is electrically connected to the control device, and the main pixel electrode has a plurality of main pixel slits where the width thereof is S. The sub pixel electrode is electrically connected to the control device, and the sub pixel electrode has a first electrode pattern and a second electrode pattern. The first electrode pattern has a plurality of first slits where the width S1 thereof is equal to or greater than the width S of the main pixel slits. The second electrode pattern has no slits or has a plurality of second slits where the width S2 thereof is less than the width S of the main pixel slits. A pixel array including the pixel structure is also provided.

Abstract: A pixel structure is provided. The pixel structure includes a control device, a main pixel electrode, and a sub pixel electrode. The main pixel electrode is electrically connected to the control device, and the main pixel electrode has a plurality of main pixel slits where the width thereof is S. The sub pixel electrode is electrically connected to the control device, and the sub pixel electrode has a first electrode pattern and a second electrode pattern. The first electrode pattern has a plurality of first slits where the width S1 thereof is equal to or greater than the width S of the main pixel slits. The second electrode pattern has no slits or has a plurality of second slits where the width S2 thereof is less than the width S of the main pixel slits. A pixel array including the pixel structure is also provided.

Abstract: A multi-view auto-stereoscopic display is provided. The multi-view auto-stereoscopic display includes a light source, a first lenticular lens, a display module, and a second lenticular lens. The light source sequentially provides a plurality of light according to a plurality of timings in a cycle. The first lenticular lens is disposed in front of the light source and respectively directs the light from the light source to travel in a plurality of directions. The display module is disposed in front of the first lenticular lens and transforms the light from the first lenticular lens into a plurality of pixel light. The second lenticular lens is disposed in front of the display module and respectively directs the pixel light toward a plurality of views.

Abstract: A pixel structure is provided. The pixel structure includes an active device, a first pixel electrode, a second pixel electrode, and a conductive line. The first pixel electrode is electrically connected to the active device. The second pixel electrode and the first pixel electrode are electrically insulated. The conductive line is located below the first pixel electrode and the second pixel electrode. The active device is electrically connected to the first pixel electrode through the conductive line. The conductive line is coupled to the second pixel electrode to form a coupling capacitance.

Abstract: A multi-view auto-stereoscopic display is provided. The multi-view auto-stereoscopic display includes a light source, a first lenticular lens, a display module, and a second lenticular lens. The light source sequentially provides a plurality of light according to a plurality of timings in a cycle. The first lenticular lens is disposed in front of the light source and respectively directs the light from the light source to travel in a plurality of directions. The display module is disposed in front of the first lenticular lens and transforms the light from the first lenticular lens into a plurality of pixel light. The second lenticular lens is disposed in front of the display module and respectively directs the pixel light toward a plurality of views.

Abstract: A video-audio playing system relating to 2-view application and a method thereof are provided. In the present invention, sound signals respectively corresponding to two independent image frames are captured and played in coordinating with the displaying of these two independent image frames. Accordingly, two users can respectively watch two image frames which are different and irrelevant each other in the same display, and further respectively hear sound effects of the respective image frames at the same time.

Abstract: A video-audio playing system relating to 2-view application and a method thereof are provided. In the present invention, sound signals respectively corresponding to two independent image frames are captured and played in coordinating with the displaying of these two independent image frames. Accordingly, two users can respectively watch two image frames which are different and irrelevant each other in the same display, and further respectively hear sound effects of the respective image frames at the same time.

Abstract: The present invention relates to a verification architecture of an infrared thermal imaging array module, which includes the following steps. Perform specification design of thermal imaging module, epitaxy, and verification of optical characteristics for calibrating epitaxial parameters. Perform a fabrication process of single-device-type sensing device and verification of changing-temperature optoelectronic measurement by measuring and calibrating at low temperatures by changing temperatures and voltages. Perform a fabrication process of focal-plane array and verification of optoelectronic uniformity and test for dark-current uniformity. Perform a fabrication process and verification of jointing and thinning the focal-plane array and the ROIC. The focal-plane sensing module and the ROIC are jointed by indium bonding, and optoelectronic signal conversion is performed using the sensing array module. Perform the verification of integrated test on thermal image quality.

Abstract: The present invention relates to a verification architecture of an infrared thermal imaging array module, which includes the following steps. Perform specification design of thermal imaging module, epitaxy, and verification of optical characteristics for calibrating epitaxial parameters. Perform a fabrication process of single-device-type sensing device and verification of changing-temperature optoelectronic measurement by measuring and calibrating at low temperatures by changing temperatures and voltages. Perform a fabrication process of focal-plane array and verification of optoelectronic uniformity and test for dark-current uniformity. Perform a fabrication process and verification of jointing and thinning the focal-plane array and the ROIC. The focal-plane sensing module and the ROIC are jointed by indium bonding, and optoelectronic signal conversion is performed using the sensing array module. Perform the verification of integrated test on thermal image quality.