Patents by Inventor Chih-Chang Yang
Chih-Chang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130242Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.Type: ApplicationFiled: October 13, 2022Publication date: April 18, 2024Inventors: Ailian Zhao, Wu-Chang Tsai, Ashim Dutta, Chih-Chao Yang
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Publication number: 20240113113Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Patent number: 11940388Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).Type: GrantFiled: March 16, 2018Date of Patent: March 26, 2024Assignee: IXENSOR CO., LTD.Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
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Publication number: 20240099035Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Wu-Chang Tsai, Ailian Zhao, Ashim Dutta, Chih-Chao Yang
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Publication number: 20240096677Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 6962107Abstract: The rotary shaft of a juicer motor is braked by engaging an arch-shaped braking piece against the peripheral sidewall of a circular block that is mounted on the rotary shaft exteriorly of the motor shell for simultaneous rotation with the rotary shaft.Type: GrantFiled: August 30, 2004Date of Patent: November 8, 2005Assignee: Lidashi Industry Co., Ltd.Inventor: Chih-Chang Yang
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Patent number: 6707197Abstract: The present invention is to provide a motor housing including two cover shells each having a hollow cover body and mounts mounted on the outer periphery thereof. The present invention is characterized in that at least one of the two cover shells has at least two ledges, which protrude outwardly from an edge of an opening of the cover body. The mounts are respectively provided on outer sides of the ledges and respectively have a first matching portion at an end of the mount of the first cover shell and a second matching portion at an end of the mount of the second cover shell. The two cover shells are connected with two ends of a stator of the motor by the ends of the mounts of the two cover shells are contacted to each other in pairs and are fastened with each other by screws.Type: GrantFiled: October 22, 2002Date of Patent: March 16, 2004Assignee: Lidashi Industry Co., Ltd.Inventor: Chih-Chang Yang
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Publication number: 20030107279Abstract: The present invention is to provide a motor housing including two cover shells each having a hollow cover body and mounts mounted on the outer periphery thereof. The present invention is characterized in that at least one of the two cover shells has at least two ledges, which protrude outwardly from an edge of an opening of the cover body. The mounts are respectively provided on outer sides of the ledges and respectively have a first matching portion at an end of the mount of the first cover shell and a second matching portion at an end of the mount of the second cover shell. The two cover shells are connected with two ends of a stator of the motor by the ends of the mounts of the two cover shells are contacted to each other in pairs and are fastened with each other by screws.Type: ApplicationFiled: October 22, 2002Publication date: June 12, 2003Applicant: LIDASHI INDUSTRY CO., LTD.Inventor: Chih-Chang Yang
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Publication number: 20020127779Abstract: A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball.Type: ApplicationFiled: March 9, 2001Publication date: September 12, 2002Inventors: Ching-Huei Su, Chih-Chang Yang, Shyh-Wei Wang, Chih-Sien Yeh
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Patent number: 6221697Abstract: A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball.Type: GrantFiled: December 30, 1999Date of Patent: April 24, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ching-Huei Su, Chih-Chang Yang, Shyh-Wei Wang, Chih-Sien Yeh